There are 3 different toolchains and languages coming together in this project:

• Intel HEX file - there are innumerable systems and tools producing and consuming this old but still useful format, most notably all the assembler, cross-assemblers etc. in 8080/Z80 ecosystem on one side, and bunch of programmers, emulators etc. on others. Any can be used in combination with this project - as long as it is "old enough" (producing just 64k address space and 00 and 01 type records only)
• VHDL (using Xilinx ISE 14.7) - to compile it all together and generate a .bit file, standard FPGA toolchain flow. Few notes:
  • No Xilinx specific "IP" components are used, in other words, "vanilla" VHDL could be recompiled for other FPGA vendors
  • Lot of VHDL code is auto-generated by the microcode-compiler as a boiler plate to include and/or copy from to create the microcoded controllers
• Microcode - this is custom "language" I "invented" to simplify creating templatized controllers. There are 3 such microcoded controllers in this project:
  • HEX2MEM - accepts stream of ASCII characters, interprets them as valid Intel HEX file stream, and generates memory write signals
  • MEM2HEX - generates memory read signals, bytes read are assembled into Intel HEX file output ASCII stream
  • TTY_Screen - accepts ASCII character stream (including some special characters such as CR, LF, CLS, HOME) and writes into a memory organized as MAXCOL columns and MAXROWS rows (in this project 80*60 for a text based VGA, but could for example be a 16*4 LCD etc.)

The software components are best explained by going through the 4 supported modes of operation:

---------------------------------------------------------------------------------------------            
--     SW7    SW6    Mode                TTY (VGA)            UART TX                7seg LED    
---------------------------------------------------------------------------------------------
--        0        0        sel_hexout        -                         Generated HEX        mem2hex debug port (or bus if nWait = 0)
--        0        1        sel_hexin        Microcode trace    Echo UART RX        hex2mem debug port (or bus if nWait = 0)
--        1        0        sel_loopback0    Echo UART RX        Echo UART RX        Baudrate (decimal)
--        1        1        sel_loopback1    Echo UART RX        Echo UART RX        UART mode    
---------------------------------------------------------------------------------------------

See other project logs for description of each of these modes of operation.