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Basics: combinational 555 logic

A project log for 555 Time

A digital clock implemented in 555 timer logic

alliedenvyAlliedEnvy 12/16/2021 at 18:100 Comments

Using our truth table, we can derive several logic gates using 555s. For combinational logic, we want to avoid any states where the RS latch remains unchanged (i.e. where Set and Reset are both 0).

!RCECTh!TrSetReset
0xxxx01
10x1101
10x0100
10xx010
1100x00
1101x01
111x010
111x100


The most basic are the 1-input gates, the buffer and the inverter.

Since !Reset drives the output low, we can put the other inputs in a state to (otherwise) drive the output high, and use !Reset as the input for our buffer. Let's pull Tr and !Th low and leave C floating. The result:

For the inverter, we can tie !R high and tie Th and !Tr together as the input:

Next, we'll do a 2-input gate. It would be nice to have a functionally complete gate. We can combine our buffer and inverter to create an inhibit gate, A&!B, which is functionally complete. I'll be calling this ANDN for brevity's sake.

Finally, since the Discharge pin is open-collector, we can tie multiple Discharge pins together with a pull-up resistor to make a wired-AND for almost free.

We could explore other gates, but this is enough.

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