So as best I can tell, everything is workable with a bodge wire here and a cut trace there on Revision 0, however, there are many things that I screwed up or didn't do optimally that I will discuss here and will include in Revision 1 going forward.
- Change the 25MHz TCXO to drive the uC directly.
- The DFU USB Bootloader cannot run using the internal RC oscillator, it requires an external oscillator.
- The uC can output the High Speed External Oscillator (or many other clock/PLLs/etc) on it's pins.
- Output HSE oscillator on pin PA8 and drive the Si5351 with that clock source.
- This still gives a good 25MHz to the clock gen which can then do its thing
- Also allows USB Bootloader to work
- Drive the clock and write lines on the DAC directly from one of the Si5351 outputs.
- The DAC datasheet says that they can be tied together.
- I had originally driven them separately from uC pins for greater flexibility (turns out this isn't necessary)
- Si5351 driving them can give a deterministic and low-jitter sampling clock.
- Feed that same signal driving the DAC clock and write lines into an external interrupt pin on the uC
- Have it drive PA0 to get a high priority external interrupt
- The DAC samples the data and select (determines whether data is for I or Q) lines at the rising edge of the clock signal.
- They only have to be stable for 2ns following the clock rising edge, which is less than one uC clock cycle.
- Setup the data and select lines, as soon as you get the clock PA0 interrupt, update the data and select lines and wait for the next clock cycle. This leads to being able to read samples out very fast using interrupt driven DMA or just calculating the next output sample very efficiently.
- Use PC10 to drive the DAC select line
- Pins PC0-PC9 drive the 10 DAC data bits.
- Previously, DAC select was driven from PA1, which is a different port.
- This required extra clock cycles as I had to write to Port C for the data and then update Port A appropriately.
- Since they are sampled by the DAC at the same time, moving DAC select to PC10 streamlines the DAC data loading by only having to write to one port one time. I or Q channels can simply be masked with
PORTC = ( DATA | ( 1 << PC10 )); // I data PORTC = ( DATA & ~( 1 << PC10 )); // Q data
- Correct the footprint for the DC jack so that the power pin isn't shorted directly to GND.
- Connect the LDET pin on the quadrature modulator to a uC input pin.
- Currently driving an LED only.
- Might be nice to know when the quad mod oscillator is locked by giving the signal to the uC so it can check lock status.
- Add an LED to the 3V3 line
- Nice to have a visual indicator that the board is at least getting power
- Because more LED is better.
- Share decoupling caps on pins that are located adjacent to each other
- Saves board space
- Makes layout a bit easier on high pin-density packages
- Make the ST-LINK header a standard 0.1" 6-pin header
- The part I chose came from the DipTrace library that had a Digikey Part number.
- While the part fits the footprint, it's an odd size and hard to make a cable harness to fit it.
- Put the user button on PB1
- If it were left on PB0, it would be hard (impossible?) to tell if an interrupt was triggered by PA0 or PB0 due to the interrupt system on the F405.
- Changing to PB1 puts it on a different interrupt channel allowing for discrimination.
Those are the issues I've discovered up to this point. I haven't finalized the Rev1 schematic yet but when I do I will post the PDF to the project page. This is also why I haven't posted the gerbers to Rev0. I don't want anyone to make a board with several known deficiencies. Look for the schematic in a few days!
Discussions
Become a Hackaday.io Member
Create an account to leave a comment. Already have an account? Log In.