This instruction provides means to load/store data at address explicitly hard coded into the instruction itself.

The instruction has length of 2 words (32 bit). As addresses themselves are 32-bit, here is a bit of compromise made -- for the loads and stores only 24 bits of address are used, therefore, there is only 16M addresses available in this mode. These are split in two equal ranges - at the top and the bottom of full address space. At the bottom there is supposed to be common RAM, and at the top the I/O should be mapped. So these transfers are primarily for I/O operations. 

The transfers are limited to be word-addressable.

Here is instruction layouts:

                     Instruction words:
                     bits of word #1      bits of word #2
Mnemonic:            FEDC BA98 7654 3210  FEDC BA98 7654 3210
LDd rX 0x01ffffff    0100 0ddd aaaa aaaa  aaaa aaaa aaaa aaaa
STd rX 0x01ffffff    0101 0sss aaaa aaaa  aaaa aaaa aaaa aaaa
LDd mpX 0x01ffffff   0100 1ddd aaaa aaaa  aaaa aaaa aaaa aaaa
STd mpX 0x01ffffff   0101 1sss aaaa aaaa  aaaa aaaa aaaa aaaa

d, s - bits of register address (X) of Destination or Source register,
 where data is loaded to from memory or stored from to memory
a - bits of hard coded memory address
rX - general purpose register
mpX - memory pointer register
0x01ffffff - explicit memory address

When writing mnemonic / asm command, the address is written fully (as byte address), but in the resulting instruction the last bit is discarded (and implicitly is set to 0), thus the instruction itself holds the word address.

For addresses in range 0x00000000 - 0x00ffffff, bottom range is targeted, for ones in range 0x01000000 - 0x01ffffff - the top range is targeted. If the address provided is bigger than 0x01ffffff, the assembler should throw error or convert to the top range.

Each range is 8M words, or 16 Mbytes.

General layout of instruction types