Instruction fetching stage is one of two main stages - fetching and execution.

We need to write old IP register(right block, top) value to TMP register (left block, top) and using full 16-bit adder do IP+1 operation.

The result of this operation as saved back to IP register.

After we got new IP, we send reading strobe to RAM, and new instruction goes to DATA line. Now we just need to write it to CMD register (Left block, bottom) and goes to execution stage.

As RAM was inited with 0x5555 and 0xAAAA values we see how on odd IP numbers Odd bits  on CMD register are flashing, and on even IP values - even bits.

Bottom line of switching boards have leds which are showing current DFATA line state and odd-even switching is observed well

With high fps camera both stages are visible very well