Post-Tapeout-Regret version: When I implemented the primes example code I noticed some shortcomings of the instructions set architecture that could be easily fixed. The updated version is here on Github, but unfortunatly did not make it on the chip.

Changes

Three changes have been introduced:

1. Allowing the NEG instruction to upgrade the carry. This allows for an easy test for accu=0 or overflow during INC/DEC macros.

2. Modifying the BCC instruction to read part of the branch target address from the accu, if the iflag is set. This allows for much easier implementation of 8 bit branch target addresses.

3. Removing JMPA as it was deemed unnecessary with the modification above.

The resulting instruction set design reduces code size, improves execution speed and even reduces the number of macrocells in the design. A clear win-win.

Updated Instruction set

Changes highlighted in red

Macros using updated instruction set

Benchmark of normal vs. plus version