The Motorola MC6809 datasheet states that the Data and Address bus signals can drive up to 4 LS TTL loads.

V1 and V2 of the Nanocomp design only have 4 chips consuming Data and Address bus signals from the CPU.
To support future expansion such as adding a video controller and video RAM will require buffers to drive the Data, Address and Control Bus signals (E Clock and R/W).
4 Buffer chips, Data Bus 1 x 74LS245, Address Bus 2 x 74LS541, Control Bus 1 x 74LS241 have been inserted onto a new breadboard between the CPU and the rest of the project.
The video of adding the bus buffer board is below.

The full Nanocomp Playlist shows creating the Breadboard computer from start to finish.

Further developments are planned. Exact Version numbers may change.

Version 4 Will expand the address space used from 32KB (A15 was not used in the original Nanocomp) to 64KB and the accessible RAM will be expanded from 4KB to 32KB.
The full 8KB of the EEPROM will also be usable.
The address decoder will be replaced using an ATMEL ATF22LV10 Programable Logic Device (PLD or GAL) which will allow more complex rules to be configured without needing lots of logic chips.

Version 5 will add a VGA compatible video card capable of 640x480 Text and basic graphics in 16 colours running on breadboards.

Version 6 will try and implement some form of Tetris type game (though without sound), so the response to "Does it run Tetris" can be yes! This spec of hardware will never be able to run Doom!

The documents, datasheets, ROM binaries, source and other files are all maintained in GitHub

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