Following work on the Aleste LX hardware and its BIOS, a draft driver architecture specification has been compiled.

The document describes a driver architecture for 8-bit banked memory systems, built on the "speed through predictability" principle. Solutions are focused on practical hardware work where every clock cycle counts.

Key features:

• Direct driver call: 17 cycles (JP + RET)
• Zero-overhead polymorphism via VTable copying
• Banked memory management with lazy switching
• Clear separation between singleton and polymorphic drivers

The specification provides direction for developing drivers for the platform: video, audio, filesystems.


Read the specification (draft)