Turns out, it would seem, that what I've off-n-on approached doing, here--in "emulating" the x86 instruction-set on a RISC architecture--is pretty much *exactly* what Intel did in switching from P5->P6, and beyond...

No kidding! Apparently x86s, since then, are RISC processors with "microcode" to process CISC instructions.

So, those instruction-handlers I started visualizing early in this project aren't attempting to "emulate" the x86 architecture any more than Intel's own x86 processors emulate x86 processors.

MICROCODE!

https://stackoverflow.com/questions/5806589/why-does-intel-hide-internal-risc-core-in-their-processors