Isetta TTL computer | Details

The idea for this design was born at the end of januari (2023).

While many homebuilt CPU's have their own, unique instruction set, I decided that for this project the CPU would use an existing instruction set. Also, I wanted to build the CPU from parts of the TTL family. That are integrated circuits, that can perform elementary logic functions. They were first used in the 60's of the previous age. I use a modern version of these circuits, that use less power.

So which instruction set to use ? The CPU inside your laptop or cellphone is much, much too complex to build. But it is possible to use an older CPU from the time when microprocessors just became available. There were two processors that can be regarded as the Beetle and the Deux Cheveaux of the beginning of the homecomputer age.

Those processors are the MOS Technology 6502 and the Zilog Z80.

The 6502 is famous because it was the heart of the Apple 1, the Apple ] [, the Commodore 64, the Nintendo NES and many others. The Z80 is well known because it was used in the TRS-80 and the ZX Spectrum, and it was widely used to run the CP/M Operating system, see also this Z80 introduction video.

So now, I had to decide whether to use the instruction set of the 6502 or that of the Z80. But then I thought... why not build a CPU that can do both ?

I did spend a few months searching for a good design that would give good performance while not using too many parts. I think the basic design is stable now (end of march 2023). I can now start with the details of the design.

BUILD A COMPUTER

A CPU is a nice thing, but on it's own it does nothing. It needs memory, power, and input and output devices. So I planned to build a full computer. Here are the specifications:

Specifications:
- runs 6502 programs
- runs Z80 / 8080 programs
- processor speed 12.5 MHz (80nS cycle time)
- 512 kByte RAM ( 8 bit wide )
- 24 bits wide microcode in 3 flash chips
- programmable (upgradable) microcode
- on-board SSD file system 32 Mbyte
- video VGA 320 x 200 pixels, 64 colors for each pixel
- video VGA 640 x 400 pixels, 16 colors for each pixel
- PS/2 keyboard connection
- PS/2 mouse connection
- Serial connection for file transfer (to Raspberri Pi)
- Connection for ESP-WROOM-02D WiFi card
- Connection for micro SD card
- real-time clock synchronized by WiFi
- sound generator
- blinkenlights (4)
- general purpose I/O
- pcb 119 x 150 mm (4.7 x 5.9 inch), 4 layers.
- powered by 5 volt USB input (250 mA)

Components:
- RAM memory chip
- Three Flash memory chips
- SPI Flash memory chip for mass storage
- 51 TTL logic chips (38 CPU, 9 Video and I/O, 4 Bankswitching)

Principles for the design:

- No microprocessor, microcontroller, SOC, FPGA, CPLD, GAL, PAL or 74181
- All components have good availability at the big distributors
- Low number of components
- No fine-pitch devices that are difficult to solder

WHAT CAN IT DO ?

At the moment (aug 2024) it can:

Run ZX Spectrum games, see Two Spectrum games running
Run Steve Wozniak's Apple 1 BASIC
Run Altair 8080 BASIC

Several more applications are planned. Having a nice operating system is one of them.

SELLING KITS

Soon there will be a KIT, to build your own Isetta !

DISCUSSION

For questions or tips/remarks you can use the discussion section at the end of the main page. Or you can join the discussion at the RetrocomputingForum / Isetta. BTW, where do you come from ?

ISETTA SYSTEM DIAGRAM

CLAIM

There are many homebuilt CPU's on the internet. But I never saw a homebuilt CPU with a Z80 instruction set (FPGA designs or emulations don't count). Therefore,

I claim that this is the very first homebuilt CPU that can execute Z80 instructions (August 2024). Until proven otherwise.

COMPUTER I/O LAYOUT

On the previous (first) PCB version, there was no mouse input.

CPU TECHNICAL DESCRIPTION

Here comes the system diagram of the CPU. Most arrows and buses represent 8 wires, that means that the information flows through the processor in units of 8 bits (a Byte).

I might as well start with explaining some of the parts.

PCH/PCL (program counter high byte and low byte)
A (Accumulator register)
T (Temporary register)
DPH/DPL (Data pointer high byte and low byte)
IR (Instruction register)

CGH Constant generator, generates only 0 (mainly for zpage addressing)
CGL Constant generator for small integer values
MBANK Bank selection system
ALU Arithmetic Logic Unit (described in project log 2)

You will miss the 6502 registers S (stack pointer) and the index registers X and Y. And you will miss the long list of registers that are inside a Z80 CPU. All those registers are in memory. A special memory section (outside the normal 64K range) is used for the registers.

In the first project log you find how the information flows through the processor.

The control section will use microcode to run the whole show. The microcode has 16 pages, 1 page is needed for the 6502 and 5 will be needed for the Z80, and the software can switch between 6502 and Z80. The microcode has room for a few more instruction sets.

[ edit: the design was simplified, see project log 13 ]

CPU LAYOUT

On the previous (first) PCB version, there was no bankswitching.

PERFORMANCE

The clock frequency of the processor will be at least 6.25 MHz (1/4 of the VGA video clock frequency).

In october 2023 I did some timing calculations and found that the processor could, after a few changes and using faster parts, reach 12.5 MHz clock speed. The first prototype will tell if my calculations are correct. [edit: Yes, it worked ! ]

For the 6502, the cpu will run many instructions in about the same number of clock cycles as a real 6502, but some instructions will take significantly more cycles. But since the clock frequency is higher, it will run programs faster than the original 2 MHz 6502.

The video output is directly generated by the CPU, so this will use a lot of CPU power. (As an option, a stand-alone video system could be used).

There will be some restrictions, decimal mode might not be implemented.

PERFORMANCE FOR Z80 MODE

Many Z80 instructions take much less cycles on Isetta than on the real Z80. These are mostly quite simple instructions, but they are used a lot. Examples are:

Note the speed of the LDIR instruction (cycles per transferred byte), accomplished by unrolling byte-copy loops in sections of eight bytes (in the microcode).

When the above instructions are used (equally, but without LDIR), the amount of cycles decreases a factor 2.2 ! That means the effective speed would be 2.2 x 12.5 = 27.5 MHz ! Instructions involving (IX+d) or (IY+d) also take about half the amount of cycles compared to Z80. The improvement is mainly caused by the fact that Isetta can access memory in a single cycle, where the Z80 needs three cycles for most memory accesses.

But not all instructions show such an improvement. Most instructions that involve shifts, stack or 8-bit arithmetic and logic take about the same amount of cycles as the Zilog.

And there are a few that are dramatically slower than on the Z80: EX AF,AF' and EX DE,HL take almost 3 times as many cycles (but EXX takes 4 cycles, same as on Z80). Exact specifications of the number of clock cycles for each instruction can be found in the file section.

So, programs will run faster than on an original 4 MHz Z80.

Information about the Z80 instructions can be found in the Z80 CPU User Manual and on the Z80info page. The officially undocumented operations on the halves of IX and IY are also supported.

PROJECT LOGS

1. Data flow in the CPU

2. The ALU of Isetta

3. Requirements for the control section

4. CPU control section

5. Control section details

6. First 6502 microcode

7. Javascript emulator runs Apple 1 BASIC

8. Another interesting BASIC to test the 8080 instructions

9. Update

10. Started KiCad layout

11. Video system