In The Beginning

The story of COMET68k really starts back in July 2021.

I had introduced a friend to the Motorola 68000 CPU and he was in the process of designing and building his first project using one of these processors. During the preceeding couple of years I had been reading the 68k's documentation during my commute to work since it was a good way to pass the time, so I was able to help him figure out the logic and explain how things worked.

Throughout this I developed enough of an itch to design and build my own 68k based system as well, something I had been wanting to do for a while, but hadn't yet started because I was consuming my time with some other projects (coincidentally 68k related so my head was already firmly in this space: Cisco 2500 Series Reverse Engineering and Cisco 1600R Series Reverse Engineering).

My first design was fairly simple - it could act as a standalone system with ROM, RAM, and a UART on board, but I also added some expansion slots that would allow additional functionality to be added. I had grand visions to add an ethernet controller and some kind of home brew video card. But I had also designed in something of a fatal flaw: there was no way for anything other than the CPU to be the bus master.

My first 68k design

So after building a couple of plug in cards for this system (including a prototype VGA card) and reaching the point where I really wanted to start work on an ethernet controller for it, but considering the controller I wanted to use would not be able to take over the bus to DMA packets to/from memory, I started to think about what I should build to replace it. I had a VMEbus backplane sitting around that I was eager to do something with, so building a Eurocard style system was high on my list of candidates.

Initial Visions

It would be about a year later when I was at EMF camp 2022 that I finally got my inspiration for what my new system should look like. There was a rummage sale at EMF camp, and in it I found an old HP JetDirect print server card which had a Motorola 68EC000 and Am79C90 ethernet controller on it (the same one I had already worked with in the Cisco 2500 reverse engineering project). I was impressed with the form factor, being not too dissimilar to a 160x100 Eurocard style board. It also had a neat trick up its sleeve which I decided I would try to copy on my new system (more in a moment).

HP JetDirect card I bought at EMF camp

I had begun to travel a lot for work at this stage, mostly by myself, and not being much of a "going out" kind of person I needed something to keep me entertained during the evenings in my hotel room when all I had was TV in a foreign language that I couldnt understand. So I set about putting together a schematic for what would become my new system.

Taking Shape

I decided to be a bit ambitious with this design, it would be a "high risk, high reward" design - the potential for failure was increased, but the reward if it all worked would be huge. Several months of on-and-off work on the schematic produced a design which I really liked, and was certainly very ambitious. I was going to attempt a design with a bunch of things I had never successfully used before, in particular DRAM, but also the ethernet controller. But the most unique feature, and the one that I was sure would cause the greatest potential for failure, was the trick that I borrowed from the HP JetDirect card.

I had originally intended to reverse engineer the JetDirect card and try to make FreeRTOS run on it, since that was my favourite thing to do with 68k based systems, and while exploring the hardware and the way it was connected I discovered something very interesting. Although there were two ROMs on the board (not unusual for a 68k system with a 16-bit data bus), the two ROMs were wired entirely in parallel. "Ok, the 68EC000 can run in 8-bit mode..." I thought, but when I investigated this more closely I discovered that the CPU was configured to run in 16-bit bus mode. More investigation was definitely required.

The card also contained a large ASIC which was responsible for a lot of glue logic and probably even contained some peripherals (I was initially trying to find a serial port, but didnt have any success). I probed around this chip with my scope and discovered the trick that it was employing to interface a 16-bit CPU to an 8-bit ROM: the ASIC would make two reads from the ROM to present a 16-bit value towards the CPU, all within a single CPU bus cycle (zero wait states!). The first read would come from an odd address and be latched onto the D7..0 half of the data bus, while the ROMs lived naturally on D15..8 and the second read from an even address would simply present the other half of the data direct to the CPU. That was incredibly neat I thought, and for a simple bit of circuitry would mean you only need to program a single ROM, and I just had to try and do this myself.

The final schematic is spread across 12 pages, and (spoiler) the first revision PCB ended up being 170x100mm in size (although I dont think I can get it any smaller).

Current Progress

As I write this it is some months after I received my first prototype PCBs, and I have built one of them and have started to bring up the system and get some working software for it. This is a summary of the initial bringup activities:

• Due to a last minute change to the PCB, all of the internal planes (6 layer PCB) ended up being shorted together, requiring some fine drilling work with a Dremel to correct
• Next I discovered that VMEbusses require a LOT of current due to the passive termination method they use, and I was initially unable to supply enough current from my bench PSU to raise the voltage high enough to configure the CPLD. I had to remove all of the buffers for the expansion bus to correct this.
• Eventually after gaining access to program the CPLD I was able to load in the design piece by piece to generate clocks, provide access to the ROMs to execute code, and implement things like an interrupt controller, bus arbiter, DRAM controller, and other things
• Wrote some test code to send and receive data via the UART, and blink some LEDs using a timer
• Adapted a serial loader utility that I had written for a previous project, and this gave me a quick way to iterate through and upload new software builds for e.g. FreeRTOS
• Got FreeRTOS running, and started to work on FreeRTOS+TCP support for the ethernet controller, but I'm hitting roadblocks at this point and currently trying to figure out why

I post tid bits every so often on Instagram (https://www.instagram.com/toms.storey/), but Im looking to establish a base where I can provide more detailed and thorough write-ups about this and my other projects.

I intend to write some more posts in the near future detailing more of the design, and taking some deeper dives into how pieces of it works. All of my design files are in github, although I have not yet made them public - I will be doing this once I am sure that the design is stable and actually works, so stay tuned for that.

In the mean time, please feel free to reach out with any comments or questions that you have, I'll do my best to respond.