New controller board still at JLPCB, so for now follows a test of one microphone from a Redpitaya which uses the same zynq7 fpga 

Testing steps from Vivado

1. Generate clk for microphone (from Xilinx PLL clk generation with counters, this is required as the PLL itself does not allow slow speeds, in this case 2.4 Mhz)

2. Get the mic data to the CIC compiler ip core as decimator

3. Send decimator mic data to BRAM

4. Read BRAM from linux and put it in a socket

5. Display in python