Yann Guidon / YGDES@Ted Yapo suggested a very unusual circuit in @esot.eric's thread
I found out that Baker (of diode clamp fame) had explored this kind of circuit:
The sweet spot seems to be between 1V and 1.1V with approximately 10ns of propagation time per inverter, and a not-too-high current draw...
I am very tempted to play with this kind of gates for this project but experience with the other technologies show that a critical gate is the MUX2 (and MUX4) which are not trivial to design with this method. I should investigate "pass gates" made of NPN and PNP transistors...
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MUX2 is (3) 2-input NANDs and an inverter - 14 transistors.
MUX4 is (9) 2-input NANDs and 2 inverters - 40 transistors.
Use small transistors :-)
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There MUST be a better way...
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Open collectors?
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In my designs, I can factor the many MUX into a common decoder and many sums-of-products (OR of ANDs). So the required MUX8 is basically many AND2 followed by a OR8 (or OR9 maybe for the immediate argument).
AND2 is quite easy, you designed one (still to be tested).
OR8 is another beast, because one "leg" is just 8 transistors in parallel, while the other is 8 transistors in series !
OR8/9 can be built with a tree of OR3 which is a reasonable compromise... But the more compact gate would be NOR3. Fortunately, NAND3 is equally easy to design...
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You can't do more than 2-input gates at 1.1V supply voltage. No way to have all those series transistors work - even with two in series, the upper one has a funny threshold.
NOR is just as easy to design as NAND, but again, only with 2-inputs.
At least so far.
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I don't want to sound "elitist" but 2-input gates don't cut it enough for me :-D NOR3 or die ? hmmm....
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