Project Details

Acceleration of Algorithms:

• Vaaman: Empowering Edge AI & ML Innovations

  Vaaman stands at the forefront of Edge AI and ML acceleration, providing a dynamic platform for groundbreaking applications. Vicharak is committed to delivering a project named 'Gati' towards custom end-to-end solutions for Vaaman, enhancing its capabilities with accelerated support for advanced algorithms. Some key applications include:

  • Object Classification: Vaaman excels in object classification tasks, leveraging FPGA parallel processing to swiftly categorize and identify objects in real-time scenarios.
  • Object Detections: Accelerated object detection algorithms enable Vaaman to detect and locate objects with remarkable precision, enhancing applications in security, surveillance, and automation.
  • Hand Gesture Detections: Vaaman's FPGA acceleration supports the rapid and accurate detection of hand gestures, opening doors to intuitive human-machine interactions and gesture-based controls.
  • Human Presence & Counters Detectors: With Vaaman, real-time detection of human presence and accurate people counting become seamless, facilitating applications in retail analytics, building management, and more.
  • Edge Machine Vision Accelerations: Vaaman transforms machine vision at the edge, accelerating the processing of visual data for applications like quality control, defect detection, and industrial automation.
  • Robotics Vision: Vaaman's FPGA capabilities contribute to the advancement of robotics vision, enhancing the perception and decision-making capabilities of robots for a wide range of tasks.

  By directly mapping these applications onto FPGAs, Vaaman optimizes resource utilization, leaving the CPU free to handle other critical tasks. This not only ensures efficient processing but also results in improved Frames Per Second (FPS), a crucial factor in real-time applications. Vicharak's commitment to developing R-CNN and potential YoloV7 acceleration support further solidifies Vaaman's position as a revolutionary solution for Edge AI and ML advancements. With Vaaman, the future of accelerated and responsive Edge AI applications is here.
  

• Cryptographic Algorithms: Swift processing of cryptographic algorithms due to Vaaman's ability to parallelize repetitive operations efficiently. FPGAs can always outperforms GPUs as well in Cryptographic Accelerations. We also have proven application where Vaaman outperforms 400$ NVIDIA GPUs, for SHA256 based algorithms.
• Video and Image Decoders: Real-time video and image processing benefit from Vaaman's parallel task handling and high-speed performance with consistent latency. Since it's a reconfigurable in nature we can have more efficient encoders and decoders available apart from standard ones.

Protocol Acceleration:

• TCP/IP & UDP: Vaaman efficiently executes communication protocols, enhancing data throughput and latency by offloading the workload from the CPU or directly processing into FPGAs, we also can run multiple parallel instances in FPGA for same protocol to maximise the throughput as well.
• VoIP Codec Acceleration: Optimize VoIP codec processing to enhance voice quality and reduce bandwidth usage, ensuring smooth and high-quality voice communication over the internet.
• Real-Time Packet Prioritization: Implement real-time packet prioritization to ensure that VoIP packets receive preferential treatment, reducing latency and ensuring a seamless communication experience.
• Dynamic Jitter Buffer Management: Accelerate the management of dynamic jitter buffers, ensuring a consistent and jitter-free audio experience during VoIP calls.
• Custom Network Protocols: Vaaman's FPGA capabilities enable the efficient acceleration of custom network protocols, tailoring communication solutions to specific industry requirements with unmatched flexibility.
• Security Protocols Optimization: Accelerate the processing of security protocols such as SSL/TLS at the hardware level, enhancing system security by offloading cryptographic operations to Vaaman's FPGA.
• Real-Time Data Compression: Vaaman optimizes bandwidth usage with real-time data compression protocols, ensuring data transfer efficiency and reduced latency in communication channels.
• Custom Encryption Schemes: Vaaman's FPGA prowess allows the development and deployment of custom encryption schemes, ensuring secure and efficient processing of sensitive information.
• Low-Latency Communication: Vaaman's FPGA-driven protocol acceleration ensures low-latency communication, a critical factor in applications where real-time responsiveness is paramount.
• IoT Protocol Support: Vaaman seamlessly supports a variety of IoT communication protocols, providing an efficient platform for the integration of IoT devices and ensuring optimal data exchange within IoT ecosystems.

Peripheral Acceleration:

• Another PCH for Processor: Vaaman extends or replicates Platform Controller Hub functionality, providing additional ports or interfaces.
• Logic Analyzer: Vaaman functions as a hardware logic analyzer, enabling real-time analysis of digital signals.
  Prototyping Software and Hardware:
• GPU and CPU Architecture: Ideal for testing new processor designs and configurations before committing to manufacturing.
• ASIC Deployment: Vaaman serves as an excellent platform for developing and testing ASIC designs, allowing for design iteration and functional verification.

Dynamic Peripheral Emulation

• Switching Between Interfaces: Vaaman can easily switch between different communication interfaces, making it adaptable to various devices and systems that use different methods to talk to each other.
• Creating Custom Hardware Platforms: Users have the freedom to configure Vaaman's FPGA to create custom hardware platforms, tailoring the system to specific needs or applications.
• Quick Testing and Prototyping: Vaaman accelerates the development process by allowing rapid testing and prototyping of peripheral systems. Engineers can experiment with different configurations to optimize functionality.
• Simulating Specialized Interfaces: Vaaman serves as an educational tool by simulating various interfaces, providing a hands-on learning experience for students and enthusiasts interested in hardware and communication protocols.
• Real-Time Testing of New Protocols: Researchers and developers can use Vaaman to test new communication protocols in real-time, offering a versatile platform for exploring and validating innovative interface designs.
• Customizing Communication for IoT Devices: Vaaman can adapt to the specific communication needs of IoT devices, allowing for the emulation of custom interfaces to enhance interoperability and data exchange in IoT ecosystems.
• Adaptive Interfaces for Robotics: Vaaman's FPGA flexibility facilitates the adaptive emulation of peripheral interfaces for robotics applications, ensuring seamless integration and high-performance communication in robotic systems.
• Efficient Emulation of Niche Protocols: Vaaman caters to niche industry solutions by efficiently emulating peripheral interfaces specific to certain domains, providing a versatile platform for industries with unique communication requirements.
• Cross-Platform Compatibility Testing: Vaaman supports cross-platform compatibility testing by emulating various peripheral interfaces, ensuring robust validation of both software and hardware components.

Linux Benefits:

Using Linux on systems with FPGAs opens up a world of possibilities, given the vast ecosystem of open-source software available.

• Retro Gaming: Build gaming systems that can run classic games, leveraging FPGAs for hardware emulation of vintage consoles.
• Remote Monitoring: Set up systems to monitor applications or hardware remotely, using the flexibility of FPGAs to interface with various sensors and systems.
• Home Server: Create a highly efficient and customizable home server with FPGA-accelerated functions.
• Ad-Blocking Router: Implement a network router with ad-blocking capabilities at the hardware level, reducing the load on the devices on your network.

Educational Tool for Chip Design and Hardware Concepts:

• Hands-on Learning: FPGAs provide a hands-on experience where students can implement and test their logic designs in the real world. This practical approach is often more engaging and informative than theoretical learning alone.
• Understanding Hardware Basics: They allow students to gain a deep understanding of how computer hardware works at a fundamental level. By programming FPGAs, students learn concepts like logic gates, memory, and I/O operations, which are the basics of computer engineering.
• Safe Environment for Experimentation: FPGAs offer a "sandbox" where students can make mistakes and learn from them without the risk of damaging expensive equipment. Because FPGAs are reprogrammable, students can iterate over their designs until they get them right.
  

SPECIFICATIONS:

CPU:

• Big.Little architecture: Dual Cortex-A72 + Quad Cortex-A53, 64-bit CPU ( Rockchip RK3399 )
• Frequency is over 1.8GHz (Big cluster)
• L1 cache
  • 48KB Icache and 32KB Dcache for each A72
  • 32KB Icache and 32KB Dcache for each A53
• L2 cache
  • 1024KB for big cluster
  • 512KB for little cluster
• Internal SRAM
  • 192KB total
  • 4KB used by bootrom when bootup

GPU:

• Mali-T864 GPU, OpenGL ES1.1/2.0/3.0/3.1, OpenCL, DX11
• Supports AFBC (ARM Frame Buffer Compression)

Memory:

• 2/4GB LPDDR4 Dedicated to CPU

Display:

• 1 x HDMI 2.0 (Micro), Support maximum 4K@60Hz display
• 1 x MIPI-DSI, Support 2560x1600@60fps output with dual channel
• 1 x USB-C DP, Support maximum 4K@60Hz display

Audio:

• 3.5mm jack with mic

Ethernet:

• 10/100/1000Mbps Ethernet (Realtek RTL8211E)

Camera:

• MIPI CSI 2 lanes via FPC connector, support up to 800MB/s bandwidth

Wireless:

• Integrated RTL8822CS Wi-Fi and BT Combo Module (6222B-SRC)
  • WiFi 2.4G+5G
  • WiFi 2T2R
  • BT5.0

PCIe:

• PCIe 2.1 (4 full-duplex lanes with 20Gbps)

USB:

• 2x USB2.0 HOST
• 1x USB3.0 HOST/OTG
• 1x USB Type-C (USB3.0 / DP Alt mode)

RTC:

• Support RTC, on-board backup battery interface

I/O:

• 1 x UART
• 2 x SPI bus
• 2 x I2C bus
• 1 x PCM/I2S
• 1 x SPDIF
• 1 x PWM
• 1 x ADC
• 6 x GPIO
• 2 x 5V DC
• 2 x 3.3V power pin

Reconfigurable chip ( FPGA - Features ) :
High-density, low-power Quantum™ architecture:

• Built on SMIC 40 nm process ( Efinix T120 )
• FPGA Resources
  • Logic Elements
    • 1,12,128
  • Embedded Memory (kbits)
    • 5,407
  • Embedded Memory Blocks (5 Kbits)
    • 1,056
  • Embedded Multipliers
    • 320 ( 18x18 bit )
• FPGA Dedicate Memory
  • DDR3L, 512MB/1GB x32 PHY with memory controller hard IP, 25.6 Gbps aggregate bandwidth
• FPGA interface blocks
  • GPIO
  • PLL
  • LVDS 800 Mbps per lane with up to 20 TX pairs and 20 RX pairs
  • MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane
  • Direct CSI-2 connectors
• Programmable high-performance I/O
  • Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces
• User-selectable voltages
  • 1.8 V, 2.5 V, and 3.3 V for bank 1B, 1C, and 2F
• Flexible on-chip clocking
  • 16 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals
  • PLL support
  • 10, 20, 25, 30, 50, and 74.25 MHz oscillators for T120F324 PLL input
• Flexible device configuration
  • Standard SPI interface (active, passive, and daisy chain)
  • JTAG interface
• 40-pin GPIO header
  • Supported with 12-pin 1 PMOD and 2 LVDS lanes or 25 GPIOs
• Fully supported by the Efinity® software, an RTL-to-bitstream compiler