Reconfigurable electronics & IO extension

Description

Reconfigurable electronics, and less mess with jumper cables? Need a chainable UART / SPI / I2C IO extender with LOTS of pins? Is it okay if it can output PWM signals as well?
The iolinker FPGA board connects any two pins (signals up to 29.56 MHz) for you, on the fly. Ideal for prototyping, self-testing and designs with many IOs.

Developing time critical embedded software and prototyping embedded solutions a lot -- sometimes with custom PCBs, sometimes without -- I noticed how much time is wasted rewiring digital signals in prototype setups; and in companies, it is costly, too, often wasting time of both a software and a hardware engineer simultaneously.

I wanted a solution that simplifies plug'n'play designs, creates flexibility and keeps my wiring in software -- version controlled. This FPGA project has been on my mind for years, and now I got some help to make it come true.

This is a preprogrammed, low-cost Lattice FPGA board + Arduino adapter.

Project Logs

Collapse

Kickstarter funding succeeded
Julian • 05/18/2017 at 17:30 • 0 comments

The Kickstarter funding succeeded a while ago!
An improved version of the iolinker board is shipping next week. It's IO mapping is slightly cleaned up and it has a MicroUSB connector for powering it. More comfy to use and test :)
With the shield adapter and our library on GitHub things are really neat to use now -- via UART, SPI or I2C:
We are on Kickstarter!
Julian • 02/15/2017 at 22:38 • 0 comments

We are now on Kickstarter and already had a great first day! http://kck.st/2kOJ15v
Complete introduction video
Julian • 02/15/2017 at 22:36 • 0 comments
FPGA board soon on Kickstarter
Julian • 02/09/2017 at 02:13 • 0 comments

Hi,
we are going live on Kickstarter next Tuesday! 3pm CEST (= 5am PST).
Teaser videos
Julian • 02/03/2017 at 20:24 • 0 comments

View all 5 project logs

Discussions

Julian wrote 05/18/2017 at 13:11

antti.lukats, thanks for your comment. You are correct about that value not making much sense. Internal oscillator clock is 66.5 MHz, so jitter and duty cycle not accounted for we should end up with ~31.6 MHz safe LNK frequency (i.e. 5.5% clock derivation and 50% Shannon-Nyquist subtracted). Not sure how to include the jitter / duty cycle part accurately? I was under the impression that was included in the synthesis constraints.

Are you sure? yes | no

Antti Lukats wrote 05/17/2017 at 13:21

you say the LNK connection can be used to signals max 29.56mhz (that is 59.12 Mbit/s) but internal oscillator i 5.5% accuracy, also you must count for some jitter and duty cycle distorion, so the limit you set in datasheet, should be either higher or lower than 29.56MHz, the exact number is for sure wrong. If you want to mux 29mhz then you must use 88.67Mhz internal oscilator clock and system clock for the multiplexer, in that case you have at least (hopefully) clock edge per 29mhz signal you mux. But if it works for 29.56, it works equally well for 29.9MHz :) so there is problem in the datasheet.

Are you sure? yes | no

Reconfigurable electronics & IO extension

Become a Hackaday.io member

Just one more thing

Description

Project Logs Collapse

Kickstarter funding succeeded

We are on Kickstarter!

Complete introduction video

FPGA board soon on Kickstarter

Teaser videos

Enjoy this project?

Discussions

Become a Hackaday.io Member

Does this project spark your interest?

Report project as inappropriate

Send message

Remove Member

Project Logs

Collapse