Validated: clock-enable logic for the internal registers. I can now set configuration registers.

Validated: IRQ selection logic works. I can set the CPLD wakeup IRQ to any specific IRQ signal. One of these was wired to the config register for testing. I can trigger the wakeup_isr by listening to the appropriate signal, and then setting that signal in the config register.

I better-pipelined some components of the transfer state-machine, and saved some CPLD complexity. As it turns out, much of my observed inconsistency was software-related, which is fixed.

Can't read from the main IMU yet...... But I think I know why. Operations are repeatable. But I still see a trailing bit in the IMU access. Fortunately, simulation shows the same thing.

Quartus reports:
Total logic elements 535 / 570 ( 94 % )
Total pins 76 / 76 ( 100 % )
UFM blocks 1 / 1 ( 100 % )