this is programming for a CPLD / FPGA the programming is the same but the pin planner is different
Schematic Version
VHDL version
Verilog version
uploads the code to the CPLD/FPGA
A project log for Rosetta stone of hardware programming
Using Hardware and software to create the programming building blocks.
this is programming for a CPLD / FPGA the programming is the same but the pin planner is different
Schematic Version
VHDL version
Verilog version
uploads the code to the CPLD/FPGA
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