Project Details

Overview

• homebrew CPU written in Verilog implemented on an FPGA
• 32-bit word-oriented stack machine architecture
• running at 77 MHz on an Arty-A7 board with four clocks per instruction
• has its own instruction set architecture, compatible with nothing
• additional IO controllers on FPGA: UART (serial console), SD-Card, VGA
• Pascal compiler written from zero
• CPU and compiler were designed together
• minimal operating system
• editor, compiler, assembler run natively
• so you can develop programs directly on the machine
• small: CPU has ~500 lines of Verilog, compiler ~9000 LoC
• compiler written in Pascal and can compile itself
• cross-compiler/-assembler can be compiled with FPC
• compiler does its own Pascal dialect with some restrictions and some extensions
• emulator available here
  

The name comes from a certain fictional monster with three heads. The prefix tri- is greek for three, and the Tridora-CPU has three stacks instead of just one like almost all other CPUs. It also has a strange mixture of features from three different eras of computing:

• a simple instruction set without integer multiply/divide like an 8-bit CPU
• speed is like a fast 16-bit CPU, also 16-bit instruction words
• 32-bit word size from the 32-bit era

It might remind you of the UCSD-P-System and early Turbo-Pascal versions.

Other inspirations were, among others, in no particular order:

• the Novix 4016 CPU (a stack machine CPU designed for Forth, mainly by Charles Moore)
• the J1 CPU by James Bowman (which is not entirely unlike the Novix 4016)
• the Lilith computer by Niklaus Wirth and his team (a stack CPU designed for Modula-2)
• the PERQ workstation (also a stack CPU designed for Pascal)
• the Magic-1 by Bill Buzbee
• the OPC by revaldinho

Source Repository

  Sources are published on Gitlab.

Supported Boards

• Arty A7-35T (with two PMODs for microSD cards and VGA output)
• Nexys A7 (planned)

Demo Videos

   See the README on Gitlab or the YouTube channel.

Pascal Language

• Wirth Pascal
• arbitrary length strings (2GB)
• safe strings (runtime information about max/current size)
• tiny sets (machine word sized), that means no SET OF CHAR
• array literals with IN-operator, which can replace most uses of SET OF CHAR
• nested procedures
• procedure/function parameters as specified in Wirth Pascal
• 32 bit software floating point with low precision (5-6 digits)
• break and exit statements, no continue yet
• static variable initialization for global variables
• non-standard file i/o (because the standard sucks, obl. XKCD reference)

Standard Library

• everything from Wirth Pascal
• some things from TP3.0
• some graphics functionality (to be expanded in the future)

Operating System

• not a real operating system, more of a program loader
• some assembly routines for I/O resident in memory
• one program image loaded at a time at a fixed address
• most parts of the operating system are contained in the program image
• file system is very primitive: only contiguous blocks, no subdirectories
• simple shell reminiscent of TP3.0, edit, compile, run programs

Building the Compiler

• you need to have FPC and Python3 installed
• on Linux, you need make installed
• in the pcomp directory, run make (or make.bat on Windows)
• on Linux, you can also run make nativeprogs and make examples

Getting the ROM image

• there are two formats for the ROM image, one for the emulator (rommon.prog) and one for building the FPGA bitstream (rom.mem)
• to get the rommon.prog file, either copy it from the tridoraemu package file or build it
• for rom.mem and rommon.prog, find both files in the lib directory after running make nativeprogs (or make.bat) in the pcomp directory (see above)

Building the FPGA bitstream

• install Vivado (known to work with 2024.2)
• install the package for your board in Vivado (Tools -> Vivado Store -> Boards)
• copy the ROM image (rom.mem) into the tridoracpu directory (see above)
• start Vivado and open the project file tridoracpu.xpr in the tridoracpu directory
• run synthesis, implementation and bitstream generation (Flow -> Generate Bitstream)
• program your device (Flow -> Open Hardware Manager), the bitstream file should be in tridoracpu/tridoracpu.runs/impl_1
• the bitstream file for (temporarily) programming your device is named top.bit, the file for flashing your device is named top.bin

Running the Emulator

See the emulator README.

Documentation

See the README on Gitlab.