There have been a few updates to the Tridora-CPU:

The clock frequency was reduced from 83MHz to 77MHz to allow for some additions to the Verilog code: I have at last implemented an instruction cache.

Now on the Tridora-CPU, the first 64KB of RAM are static RAM (created from BRAM). The rest is DRAM (256MB on the Arty-A7), and this is accessed via a memory controller generated my MIG, the Memory Interface Generator in Vivado. This memory controller has a latency of 21 cycles and always transfers at least 16 bytes. Good for bursting data to cache lines in modern CPUs, not optimal for my simplicistic design.

To make matters worse, the CPU uses 32-bit words, but 16-bit instructions. So for an instruction fetch, the CPU reads 32 bits, then throws half of them away to get the instruction. For the next instruction, it will fetch the same 32 bits again, then throw the other half away to get the second instruction in that 32 bit word. This does not matter when executing out of SRAM, but is really bad when executing out of DRAM.

So an instruction cache was needed. I added a signal from the CPU that indicates an instruction fetch (in contrast to a data read/write), and implemented a simple caching mechanism that just stores the 16 bytes from the last read, and satisfies the read request from that if the read address is in the same 16-byte segment.

In the optimal case, 8 instructions will now take 53 clock cycles instead of 200.

I have created a benchmark program in Pascal for some measurements, and in some benchmarks the improvement is about factor two.

In others, it is less noticable, depending on the amount of data memory accesses which are not cached. Also, some benchmarks exercise operations which are assembly subroutines which reside in SRAM, for example, integer multiplication or all floating point operations.

Many programs do not run noticably faster though, because they fit inside the first 64KB of RAM. For the benchmark to show any difference, I had to hack the assembly code to move the code above the 64KB boundary.

The full benchmark results can be seen here: https://gitlab.com/slederer/Tridora-CPU/-/raw/main/examples/benchmarks.results.text

This is the benchmark source code: https://gitlab.com/slederer/Tridora-CPU/-/raw/main/examples/benchmarks.pas