Today I was contacted by [Nigel] asking about interrupt and PIO details, especially regarding interboard communications.  [Nigel] is attempting an emulator of the system, but presently it is 'hanging' early in the boot process and hypothesized that the main board is waiting on the io board.

I replied that I had not really looked into that part of the system, figuring that the I/O board would be inscrutable without a schematic, but that I would take a peek.

[Nigel] shared what he knew of the hardware; i.e.port mappings of the various I/O chips.  I was impressed with such detail, and as it turns out there was a historical effort to emulate this system which was not completed.

I did an initial disassembly of those ROMs, and found the init code for the CTCs, PIOs, and PPIs.  This jibed with Nigel's existing port mapping.  (This also saved me some time, because otherwise I'd have to look at the byte sequence and see for which device this made sense.  I did that for the main board.)

The memory map is straightforward:  32 KiB ROM followed by 32 KiB RAM.

[Nigel] hypothesized there was some 'shared memory' scheme between the two boards.  This was based on comments in the non-functioning prior emulator.  I was skeptical of this -- it would certainly be pretty exotic, and just the board shot alone doesn't seem to have the needed support circuitry. But I'm open to being wrong.  You have to be open to being wrong when reverse-engineering.  You're always wrong until you progressively become right.