This weekend we finally got around to do all testing on the IRQ prototype board, in order to be able to get the stage2 board. There were some difficulties (mostly bad thinking from our side) but we managed to get it running with some small modifications. So now, with some minor updates we were able to order a batch of stage2 boards. One major step towards the complete system.

And you know what? I was actually contacted by a representative from PCBWay who showed interest in this project, so now they are actually sponsoring it! I'm really looking forward to this!

So what did we need to update after prototype testing? 

The output (the IRQ signal) is active high and the processor expects an active low signal, so here we got to insert the extra unused NOR-gate to invert it.

The clock pulse was connected to an inverted read signal which means that it will not clock in an released interrupt in the register without reading it again. This was sorted by clocking it with Q, since that is a quarter pulse earlier than the read, it will always have fresh data in the register upon read.

OE was connected to the read signal and since it is an active low input it needed to be inverted. So we reused the NOR-gate used for the previously used clock pulse.

We also found that the NAND gates collecting the irq-levels (U5) was out of order so the interrupts came in in the wrong order.