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• Inital SiC JFET Test

  Collin Matthews • 3 hours ago • 0 comments

  I recently procured some United SiC JFETs, which looked to be a solid answer for any active region high voltage or high current project. I figured they may be a good start for this amplifier, and I could drive them in a trivial cascode configuration with a high voltage supply and signal generator. Basically in a few hours I could see how they performed.

  First I found a simulation model, and discovered the high frequency performance was not amazing. I assume this is due to drain to gate capacitance, and even in cascode it provided a challenge. The other issue is a resistive only coupled output would limit my "high voltage" to a few hundred volts.

  This was enough for me to construct a circuit on a bare PCB for testing.

  I then attempted to add a transformer. I initially used a simple model that looked promising, but upon constructing a U-Core ferrite transformer with a 1:3 step-up, and measuring the parasitics, I found the simulation and real life to come shockingly close, both with poor performance... 

  The low frequency was limited by the primary inductance of the transformer (Lack there of), while the high frequency was limited by the parasitics of the transformer and JFET. Unfortunately fixing one of those issues would make the opposite worse. This resulted in a very narrow band of operation.

  Basically I needed to really go back to the drawing board and fix both the silicon and the transformer. I ended up finding some 400V rated depletion mode NFETs (DN2540). People commonly think it is easy to find high voltage FETs, but 99% of the FETs you see online are designed for switching and can not be operated in the linear region for use in amplifiers like this.
  

  These new FETs had less parasitic capacitance, although a lower voltage and power rating as well. Then in an effort to improve the transformer, I found a unique ferrite product from a German company (VACUUMSCHMELZE). It has significantly higher permeability then typical cores. This allowed more primary inductance with 1/3 the turns of the U-Core I was using. This then also resulted in less leakage inductance and lower inter-winding capacitance.

  See the next log for more info.

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