The next compute-in-memory operation to implement would be some kind of boolean operation between two or three rows. This can be achieved by aborting row loading before it has been completely refreshed and then immediately open another row, so that the charges from the first and second row can combine on the bitlines.

This requires very fast timing. Unfortunately it turned out that it is not possible to toggle GPIOs on the CH32V003 in a single cycle using bit banging, the minimum is two cycles. 

I spent quite some time investigating this issue. There are various unfortunate combinations of flash waitstates, lack of instruction buffers and bus contention that lead to this. 

Experiments and more details are here:
https://github.com/cpldcpu/DRAM_exploration/blob/master/instruction_timing/README.mdSo, that means I have to look for an alternative approach to generating the necessary timing.