Over at the #miniMAC project, there was this log 108. Error correction and the realisation that the channel coding should be done directly in ternary. The encoder is pretty straight-forward (see above log) but the decoder is a different beast. Still, I know it's possible since GbEthernet uses it (TCM) over 4 simultaneous channels so there should be a way, right ?

http://pl91.ddns.net/viterbi/algrthms2.html has some good ideas for the binary case and I don't want the system to get out of hand (complexity, size, latency). But I'm somehow glad that others have already studied the subject of conversion to ternary.

• 2023 https://www.ijfmr.com/papers/2023/2/1757.pdf "Design of Ternary Convolutional Code Using
  Reconfigurable Architecture"
•  2017-2021 : https://dspace.library.uvic.ca/server/api/core/bitstreams/faafcf78-7e00-4fe4-b599-95f97f9cafa5/content by Bharath Rao Madela
• https://arxiv.org/pdf/2209.01360  Henri Mertens and Marc Van Droogenbroeck: "Error-rate in Viterbi decoding of a duobinary signal in presence of noise and distortions: theory and simulation", 2022 
• 2002-2014 Khmaies Ouahada: several publications starting from the thesis, university work and more later. Found also on ResearchGate, great reading, that seems to converge to several of my conclusions.
• https://www.researchgate.net/publication/266389989_Viterbi_Decoding_of_Ternary_Line_Codes
• https://www.vodafone-chair.org/pbls/legacy/gerhard-fettweis/High-rate_Viterbi_processor_a_systolic_array_solution.pdf (not ternary though)

So the subject is not novel (which is both sad and great). I have actual data to crunch. Note that several studies just do the FPGA compilation and simulation tests but real field tests are lacking, I would love to see the actually measured waveforms. Where are the oscilloscopes ?

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"Soft-decision Viterbi" seems to point to using more input bits, like a 3- or 4-bit flash ADC but this becomes impractical. Actually, that's where TCM leads us. And with 2 input bits, that's a 4-bit ADC. If the 2 differential inputs are used as 4 single-ended ones, that's a 4-bit, 16-level Flash ADC.

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So far the idea is to do the DSP part in ternary though I doubt I could achieve Viterbi decoding at 50M trits/second (equivalent to about 60Mbps of useful bandwidth). Some parallelism becomes necessary. And other tricks too.

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Anyway, using a convolution code solves quite a few things and the Viterbi decoder is somehow simplified (a tiny bit) because the binary-to-ternary (3B2T) conversion leaves one code unused (8 out of 9 codes). However the mechanism against baseline wander goes out of the window. Unless I can make a wander-reduction mechanism that also acts as a convolution code ? Then the extra data works for 2 effects ?