The QSDE state machine is replaced by QSLD :

• Quiet (no signal on the line, disconnected or at rest, or request to close the line)
• Synching (trying to advertise presence, or presence detected)
• Locked (acknowledge that PLLs are synced, ready to send data, or data not ready)
• Data (data transmitted or received)

Still 4 simple states, still 2 bits.

The interesting part is that this pair of bits is both a state and a command, so it's present at the input and output of the units (MAC, PHY ...)

(insert state machine diagram)

Errors go back to Synching, and Locked is used when no data is present but the link remains active (sort of Idle but not to be confused with Quiet).

MAC-PHY link

Due to the usual high cost/limitation of pins, the link uses dual-edged clock and keeps the meta/control information to the minimum. All the communication use the QSLD state, which uses only one wire in DDR.

For the PHY-MAC link, we get 5 wires :

• CLK active high then low
• QSLD sampled 2× : CLK rising => b0, falling => b1
• Data[2:0] expanded to 6 bits, CLK rising => Data[2:0], falling => Data[5:3]

Notable feature : the QSLD wire toggles only in Sync or Locked states. If tied to 0 it's quiet/disabled, if 1 then data is flowing (the desired state).

3 cycles are required to transmit 18 bits. There is no clear start (no room for a framing bit) so it is implied by going from the Locked state to the Data state. This resets a free-running 3-state counter, incremented for each new Data cycle. Going back from D to L when the counter is not 0 is an error and the peer will reply with Sync.

When in states Q, S or L, the data bits are "don't care" though they could be used to send configuration or auxiliary data, one day.

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MAC-host link

Same constraints so a DDR interface is used as well. But due to the larger and slower bus, the data path is 8 bits. An extra bit works as Control/Data flag during one phase but is not used in the other phase (for now).

Total: 11 wires

• CLK active high then low
• QSLD sampled 2× : CLK rising => b0, falling => b1
• Data[7:0] expanded to 16 bits, CLK rising => Data[7:0], falling => Data[15:8]
• C/D : sampled at rising edge, added to the 16 data bits. The falling edge value would be used only during the first tests to emulate the parity bit.

A whole word is transmitted every cycle. There is no counter to care of. The QSLD state is per-word.

Since everything is "clock sourced" and each device in the chain has their own local oscillator, the overall system is considered asynchronous.

Normally the transmitter should do its best to keep the link in Data mode, resorting to the Control type words to fill the bandwidth with padding control words. The Locked state may bypass the scrambler and prolonged L state would affect EMI & BLW. But for now, let's consider we link two MAC together without going through a PHY (which is actually the current situation).

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The "parallel" interface amounts to 9 bits per word, the "nibble" interface to 3 bits, so there is a 3× speed difference. The circuits need (double-)buffering, probably a "Hold" signal...

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