What a great amount of fun this has been!

I set up a test environment for the new automatic UART detector and logger, and as expected, it didn't work like the sim at all!

I did a lot of work upfront to create a good analysis setup for monitoring the FPGA UART detector design--see the analysis screen capture in the gallery. It is showing a 460800 baud signal RX and TX, and below it are internal FPGA test signals from the UART detector. You can see the 8X baud rate pulses, the pulse counter, the incoming signal edge detector (with metastable handling on the front end) and the last signal is the module detecting a 460800 baud rate. 

It didn't work at first for the obvious reason (obvious to anybody but me until I saw it, anyway)--any double hi or low serial bit at 460800 baud will look like 230400, so the detector was constantly getting contradictory outputs. Easy to fix--the highest detected baud rate is always accepted, and from then on, no lower baud rates are allowed. The serial polarity indicator worked like a champ from the get go--by determining whether the high level or low level had the longest time between edges I was able to set the polarity. More testing to do, but it's looking really nice!

Now I need to work on the serial character stream display--it's not working yet.