A perfect example is the burst-length option in SDRAM (which, stupidly, I hadn't really thought could apply to DDR, and others thereafter, until just now).

PC-66/100/133 SDRAM officially has burst lengths of 4 or 8 bytes/columns. But I have experimented with *numerous* from *numerous* manufacturers and have found that they *all* support bursting of the entire row (often 512 or 1024 bytes, but I've encountered  as low as 128 and as high as 2048).

I used this technique extensively in projects like #sdramThingZero - 133MS/s 32-bit Logic Analyzer 

....

The key, here, is that many of the datasheets for the chips *don't* list row-burst as an option.

 Many brands seem to write their datasheets to match generic specs, rather than actually documenting what their product is capable of. Weird.

...

There are many other tangents I could go on, regarding how it seems SDRAM was somewhat intentionally designed with *backwards*-compatibility with *non*-synchronous DRAM e.g. that from 72-pin SIMMs... that never really caught-on since dedicated controllers quickly became commonplace...

But one example is that all the instructions (except the Load Mode Register, ironically) are explicitely-allowed to occur repeatedly back-to-back. The effect of which is akin to holding the Read-pin on normal DRAM... it just keeps outputting the same data until it's released; *asynchronously*. Except, of course, in the case of SDRAM, it just waits to release until the approrpriate number of clock-cycles later.

But, you can imagine, if the SDRAM is running at 133MHz and it's replacing a DRAM in a PCXT running at 4.88MHz, then for all intents and purposes, the SDRAM treated asynchronously would look asynchronous to the 8088... And... frankly... 

I think there was intent behind that. Long forgotten intent

I've documented a lot of my SDRAM findings elsewhere on this site... And right now I'm excited about a new finding regarding LCDs, so I'mma get to that next.

(Am also reminded of some great hackery I've seen elsewhere... was it EDO DRAM can be tricked to look like FPM (or vice-versa?) by simply repurposing one of the pins... So, the only thing keeping them from being drop-in compatible is the fact they're usually soldered onto a carrier-board for one specific mode... Great discovery that opens a lot of doors for retrocomputing. But part of me thinks it was actually by-design, and was probably even documented that way in early datasheets, but long forgotten thereafter as the newer tech replaced the older)