As it is, the circuit oscillates far too fast for what we want. We thus need a way to slow it down. One way is to add an RC circuit on the output of each stage : capacitor take time to charge, and this time retards the propagation of the output state of a node to the following input.

See the updated schematic of the base node with such a RC circuit.

R3 and C1 are chosen accordingly to the timing required. The time constant of an RC circuit is given by the following formula :

with: 
    τ in seconds
    R in ohms
    C in farad

For nine nodes in the circuit, the individual time needed for one gate would be 1/9 = 0.111s. For a 1k resistor, it gives a 111uF capacitor value. I've settled for a 100uF cap, and a 2 kohm potentiometer to make room for fine adjustment. However, I failed to account for quite a few things :
    capacitor charges through the pull-up resistor as well.
    capacitor discharges through the input resistor.
    transistor is saturated when Vbe is above 0.65V.
    low level on output is 0.2V, not 0V.
Those forgettings causes the chosen values to be a bit faster than intended, but we are close enough to one second.