I just made a simulation model for the bucket logic.

In the original Trump Card schematic, I noticed (what seems) a redundancy with the signal /BIOW at IC30 pin 13 and IC33 pin 12. That may explain the 470pF capacitor at the output of IC28 pin 9.

While the original circuit modif may not be trivial, the CPLD version would be much easier to correct, and no need for capacitor.