Code

UART Receive Module

Converts the GP-01’s single-bit data into 8-bit data.

module  uart_rx

#(

    parameter   UART_BPS    =   'd9600,         // Baud rate

    parameter   CLK_FREQ    =   'd50_000_000    // Clock frequency

)

(

    input   wire            sys_clk     ,   // System clock 50MHz

    input   wire            sys_rst_n   ,   // Global reset

    input   wire            rx          ,   // UART receive data

 

    output  reg     [7:0]   po_data     ,   // 8-bit parallel output data

    output  reg             po_flag         // Data valid flag

);

//********************************************************************////****************** Parameter and Internal Signal *******************////********************************************************************////localparam    define

localparam  BAUD_CNT_MAX    =   CLK_FREQ/UART_BPS   ;

//reg   define

reg         rx_reg1     ;

reg         rx_reg2     ;

reg         rx_reg3     ;

reg         start_nedge ;

reg         work_en     ;

reg [12:0]  baud_cnt    ;

reg         bit_flag    ;

reg [3:0]   bit_cnt     ;

reg [7:0]   rx_data     ;

reg         rx_flag     ;

//********************************************************************////***************************** Main Code ****************************////***************************************

// Insert two-stage registers for data synchronization to eliminate metastability

// rx_reg1: First-stage register, reset to 1 when idle

always@(posedge sys_clk or negedge sys_rst_n)

    if(sys_rst_n == 1'b0)

        rx_reg1 <= 1'b1;

    else

        rx_reg1 <= rx;

 

// rx_reg2: Second-stage register, reset to 1 when idle

always@(posedge sys_clk or negedge sys_rst_n)

    if(sys_rst_n == 1'b0)

        rx_reg2 <= 1'b1;

    else

        rx_reg2 <= rx_reg1;

// rx_reg3: Together with rx_reg2, forms the falling-edge detection

always@(posedge sys_clk or negedge sys_rst_n)

    if(sys_rst_n == 1'b0)

        rx_reg3 <= 1'b1;

    else

        rx_reg3 <= rx_reg2;

 

// start_nedge: Generates a one-clock-cycle high pulse when a falling edge is detected

always@(posedge sys_clk or negedge sys_rst_n)

    if(sys_rst_n == 1'b0)

        start_nedge <= 1'b0;

    else    if((~rx_reg2)...