TL;DR

I extended the CPU from 16 to 32 bits to specifically run the following benchmark, proposed by Noel's Retro Lab:

I was most interested how 32-bit Basic CPU is performing relative to modern "retro" computers. They have fixed CPU clock, so I adjusted or interpolated results from runs seen above for comparison:

While these numbers favor the Basic CPU, in reality the systems above can run much more feature rich variants of Basic, with graphics, sounds, functions etc. while Basic CPU has only USR/PEEK/POKE at disposal. Still, not too bad for running an interpreter from 50 years ago on FPGA from 10 years ago. 

Extending from 16 to 32 bits

Most Basic variants support to 16-bit 2's complement integers. They are fine for many use cases, and arithmetic with them is reasonably fast even on 8-bit CPUs. Unfortunately, Tiny Basic has no Floating point support, so having just 16-bit integer can be limiting. So I decided to expand the CPU from 16 to 32-bits. The design goals were:

1. No  changes to the interpreter - both original and extended interpreters can run on 16 and 32 versions
2. Minimal changes to microcode - only where absolutely needed, for example 32-bit 2's complement integer convert to up to 10 decimal digits, while 16-bit to 6 so some loop counters etc. must be changed
3. Changes to hardware are ok, but avoid any special case if/then if possible

For #3, there were two possibilities:

1. Run-time support for 16/32 bit switch. A bit like 65802 vs 65C02 - a flag or a pin flips the CPU to 32-bit mode. 
2. Build-time support for 16/32 bit generation of the CPU itself. 

I chose #2 as it seemed as easier implementation, and also because if I continue this project it is unlikely I would go back to 16 bit (next logical step is implementing Floating Point, which is viable only on 32-bit data / variables), and in that case all the complexities of supporting 16/32 will be present in the CPU, bloating the FPGA footprint and won't be needed right after boot into 32-bit mode.

Parametric VHDL design

The general idea here is to use feature of hardware description language to generate the registers and interconnections using parameters consumed during compile time. This code handles about 80% of what is needed to compile the design to be either 16 or 32 bit CPU:

-- generics
constant MSB_DOUBLE: positive := (MSB + 1) * 2 - 1;                            -- 31 / 63
constant MSB_HALF: positive := (MSB + 1) / 2 - 1;                                -- 7 / 15
constant ZERO: std_logic_vector(MSB downto 0) := (others => '0');            -- X"0000" / X"00000000"
constant MINUS_ONE: std_logic_vector(MSB downto 0) := (others => '1');    -- X"FFFF" / X"FFFFFFFF"
constant BITCNT: std_logic_vector(4 downto 0) := std_logic_vector(to_unsigned(MSB, 5));        -- 15 / 31
alias IS_CPU32: std_logic is BITCNT(4);                                                                        -- '0' / '1'
constant STEPCNT: std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(MSB + 1, 8)); -- X"10" / X"20"
constant BCDDIGITS: positive := (MSB + 9) / 4;     -- 6 / 10
constant CP_OFF: positive := MSB_HALF + 1;        -- 8 / 16
type ram16xHalf is array (0 to 15) of std_logic_vector(MSB_HALF downto 0);
type ram32xFull is array (0 to 31) of std_logic_vector(MSB downto 0);

During build-time, parameter MSB is passed in as either 15 or 31, and then based on that various other values are determined, for example BITCNT which determines the number of steps during division, etc. 

The above is not sufficient to create a functioning 32-bit CPU. The main problem is that the memory interface toward RAM that holds Basic code and input line remains 16 bit address / 8 bit data (64kb RAM), Basic line numbers are still meaningful only to 16 bits (due to the convention how Basic lines are stored) etc. The table below summarizes the major differences that had to be addressed with generating the 32 vs. 16-bit CPU.

r_is_zero <= r_is_zero_full when (IL_OP = OP_DV) else r_is_zero_16;                    

...

-- for divide instruction check full R to prevent divide by 0, for other operations R is memory address or line number (16 bit)
r_is_zero_full <=     '1' when (R = ZERO) else '0';
r_is_zero_16 <=        '1' when (R(15 downto 0) = X"0000") else '0';    

R(MSB downto 16) <= (others => '0');

-- index offsets for 2 (16-bit) or 4 (32-bit) byte elements    

T_offset <= (T(13 downto 0) & "01") when (IS_CPU32 = '1') else (T(14 downto 0) & '1');