Intel 4004 Microprocessor Recreation

A cycle-accurate recreation of Federico Faggin's pioneering 4004 microprocessor in open-source silicon, alongside modern evolutionary architectures.

4004 Die Photo Real die shot of the historic Intel 4004, the world's first microprocessor

🎯 Project Goals

This project recreates the complete Intel MCS-4 system while simultaneously exploring the "what ifs" of computer architecture history. The goals are:

  1. Historical Preservation: Document and preserve the 4004's architecture for future generations
  2. Evolutionary Exploration: Design pipelined and RISC variants to demonstrate architectural progression
  3. Education: Provide a working, understandable example of early microprocessor design
  4. Physical Silicon: Manufacture actual working chips through Efabless/SkyWater

📖 The Story

The Intel 4004, designed by Federico Faggin in 1971, was the world's first single-chip microprocessor. It contained 2,300 transistors and enabled the microcomputer revolution.

This recreation honors Faggin's pioneering work by bringing his design into the modern era of open-source silicon. I am traveling to Italy to visit Olivetti (where Faggin started his career), his hometown of Vicenza, and to study the history that led to this revolutionary chip.

Read the blog

For a more detailed look check out the repo

🧪 Experimental Cores

Beyond the faithful recreation, this project includes two novel cores that explore alternative histories and modern design principles:

Core B: Pipelined 4004 ("The What-If")

A high-performance reimagining of the 4004. It asks the question: If the 1971 engineers had a larger transistor budget, how fast could they have made this chip?

  • Architecture: 5-Stage Pipeline (Fetch, Decode, Execute, Memory, Writeback)
  • Datapath: Full 4-bit parallel execution (replacing the original serial ALU)
  • Compatibility: 100% binary compatible with the original 4004 ISA and bus
  • Performance: Targets significantly higher IPC (Instructions Per Cycle)

Core C: RISC-4

A clean-slate, novel 4-bit architecture designed for modern efficiency and compiler friendliness.

  • Architecture: 5-Stage Pipeline with Von Neumann memory model
  • ISA: Custom fixed-width RISC (Load/Store architecture)
  • Features: Simplified control logic, unified memory bus, and modern hazard handling
  • Specification: View the RISC-4 ISA Repo →