In one of the previous logs I pledged to find out what are tolerances of RTD2660H chip inside the monitor regarding VGA signals it can recognize as valid.

I started with the most VGA signal there is -- 640*480 pixels at 60 frames per second. Though the image is 480 lines in height, the whole frame, taking into account blanking and Vsync has 525 lines in it. As for the number of pixels per line -- the value is almost arbitrary -- the video signal itself is analog, and there is no intrinsic discretisation of the line into separate pixels. The standard of 640 pixels per line is chosen such that pixels are "square" on monitors (on CRTs they are more round than square though). What actually matters is correct timing of horizontal synchronization pulse, and of blanking intervals.

The first experiment is checking the limits on vertical sync pulse width. The standard one is 2 lines. But I found that this monitor is just fine with Vsync pulse of single line. On the bigger side there seemingly no hard limit on vSync width. For the value of 256 lines the image gitches funnily, although for higher and lower values, there is no such glitching.

Starting with 263 lines (i.e. the LOW vsync pulse becomes just longer than half of the frame), the synchronization circuit flips, and image is split in two, with lower half on top and top half in the bottom.

 With further increase of the length of low pulse, the image is shifted upwards, and when polarity of Vsync is completely reversed, meaning that instead of active LOW pulse duration of 2 lines there is an active HIGH one of the same length, the image is displayed correctly.

IN CONCLUSION, it seems that RTD2660H chip handling decoding of VGA signal does not enforce strict polarity rules on vertical synchronization pulse, and instead treats the start of the shorter phase as trigger for starting a new frame.