Building an open-source, low-cost 10.5 GHz phased array radar with phased array antenna and Pulse LFM modulation—available in 3km and 20km range versions. For researchers, drone developers, and serious SDR enthusiasts.

The Vision:

Phased array radar is the gold standard for electronic beam steering—enabling instant tracking, weather resilience, and precision sensing. Yet today, even entry-level systems cost more than $250,000, locking this technology away from researchers, students, and independent innovators.

I'm building the “AERIS-10” to change that. An open source “32x16 element X-band phased array radar” with full electronic beam steering, Pulse Linear Frequency Modulation (LFM) at a fraction of traditional cost.

Why This Matters

Today, anyone who needs advanced radar capability faces three flawed options, each with unacceptable tradeoffs.

Military surplus equipment might seem like a bargain at $10,000-50,000, but you're buying decades-old technology. These systems use mechanical scanning only—no electronic beam steering. They're analog, completely obsolete, and come with no API or modern interface. When they break (and they will), there are no spare parts.

Commercial radar systems deliver modern performance but at an astronomical price: $250,000 to over $1 million. Even at that cost, you're getting a closed "black box." The firmware is locked, the beam patterns are fixed, and there's no way to modify or extend the system for your specific research needs. You're renting capability, not owning technology you can build upon.

Building from scratch is the path for well-funded research labs or obsessive hobbyists—but it's a multi-year undertaking requiring a deep team with specialized expertise across RF, FPGA programming, signal processing, and mechanical engineering. Just the test equipment (spectrum analyzers, network analyzers) costs more than $50,000. And building a phased array from discrete components? For a small team, it's nearly impossible to achieve consistent, calibrated performance.

The result: A massive capability gap. There is no affordable, programmable, electronically-scanned radar platform for researchers, educators, and innovators who want to push the boundaries of what's possible with radar.

AERIS-10 changes this. By combining modern SDR technology with an innovative system, we deliver true phased array performance at 90-95% below commercial alternatives—with open APIs that let you build your own applications.

Technical Specifications:

Current Status: Alpha Prototype

For sake of testing, validating and optimizing the cost of the prototype, this late has been designed using one PCB for: - The Power supply management - The Digital components - The Analog and mixed signal components - The RF parts

This won’t be the case for the mass production system, where separated modules would be used to reduce EMI and enhance the signals integrity; also a more professional clock source and frequency synthesizer would be used. The new schematics, PCB layout and firmware are already available

Understanding the System Hardware:

The AERIS-10 main sub-systems are:

Understanding the System Software and Operational Flow:

The AERIS-10 radar system is built around three core processing elements working in concert: an STM32 microcontroller handling system management and peripherals, an FPGA executing real-time signal processing, and a Graphical User Interface (GUI) for user control and data visualization. The following describes the complete boot sequence and operational loop that governs how the system wakes, calibrates, and begins scanning.

System Boot and Initialization

When power is first applied, the STM32 microcontroller begins a carefully sequenced startup routine designed to bring all subsystems online in the correct order, ensuring stable power and clock references before any RF activity begins.

The first critical step is waiting for the OCXO (Oven-Controlled Crystal Oscillator) to reach thermal stability. This high-precision frequency reference requires approximately three minutes to warm up and stabilize—without this wait, the entire radar's frequency accuracy would drift, compromising range resolution and target detection.

Once the OCXO is stable, the STM32 manages voltage sequencing for the system's clock generator, the AD9523. This ensures that power rails reach their correct levels in the proper order before the device is initialized. The STM32 then configures the AD9523, setting up the planned clock distribution that will drive the FPGA and all RF components with precise, phase-aligned timing.

With clocks established, the STM32 sequences power for the FPGA itself, then proceeds to initialize the remaining peripheral systems:

At this point, all hardware is ready and the system enters a waiting state, listening for the start command from the GUI.

GUI Connection and System Arming

The operator interacts with the system through a custom Graphical User Interface running on a connected computer. When the user is ready to begin operation, they press the Start button on the GUI.

The GUI immediately transmits a specific start flag packet to the STM32—a predefined sequence of bytes {23, 46, 158, 237} that serves as a handshake to confirm communication is established. Following this flag, the GUI sends the full operational settings for the upcoming radar scan (waveform parameters, scan pattern, range settings, etc.).

The STM32 acknowledges these settings and begins actively monitoring the GPS data stream. It waits for a valid data lock, then begins sending modulated position streams back to the GUI containing longitude, latitude, and altitude information. The GUI receives these streams and uses the coordinates to center its map display on the radar's current location—giving the operator immediate spatial context for any detected targets.

Attitude Determination and Mechanical Alignment

While maintaining GPS position updates, the STM32 continuously reads raw data from the IMU and barometer. It processes the IMU data to calculate pitch, roll, and yaw angles, while the barometer provides a secondary altitude reference.

With yaw (heading) known, the STM32 commands the stepper motor to rotate the antenna assembly to align with yaw = 0° (typically true north or a defined reference). This mechanical alignment ensures that all subsequent electronically-steered beams are referenced to a consistent absolute direction.

Transmit and Receive Chain Configuration

Before any radar pulses are sent, the RF front-end must be precisely tuned. The STM32 configures the two ADF4382 frequency synthesizers—one set to the transmit frequency, the other to the receive frequency. Critically, it then executes a phase synchronization routine between these two synthesizers, ensuring that transmit and receive local oscillators are phase-coherent. This coherence is essential for Doppler processing and coherent pulse compression.

The Scanning Loop: A Three-Level Nested Structure

The AERIS-10's scanning pattern is organized as a three-level nested loop, controlling:

This structure allows the system to build a complete volumetric scan through a combination of electronic beam steering (fast, within the pulse repetition interval) and mechanical rotation (slow, covering 360 degrees).

Loop Variables Defined

The Operational Loop

The loop begins with the STM32 commanding the stepper motor to move to the first azimuth position (y=1). Once the mechanical position is settled:

Loop Iteration and Scan Completion

After completing the processing for chirp m, the system increments m and returns to step 34 (DAC chirp generation). This continues until m exceeds 32, at which point:

When n exceeds 32 (all electronic beam positions completed), then:

This continuous loop builds a complete 3D radar picture, with electronic steering providing fast elevation/azimuth coverage and mechanical rotation providing full 360-degree azimuth scanning.

Summary

The AERIS-10's operational flow represents a sophisticated orchestration of multiple subsystems:

This division of labor allows each processor to focus on what it does best, creating a coherent, high-performance radar system that remains flexible and programmable through its open architecture.

What's Working:

What's in Progress:

Get Involved:

I'm actively seeking:

-              Beta testers:  (university researchers, drone startups, advanced makers)

-              RF engineers to review designs

-              FPGA developers for signal processing optimization

-              Software developers for the Python/C++ SDK