Aegis is a fully open-source FPGA, from the silicon up.

Open-source FPGA efforts have made huge strides: projects like Project IceStorm and Apicula reverse-engineer proprietary bitstream formats, OpenFPGA and FABulous generate open FPGA fabric from architecture descriptions, and Cologne Chip's GateMate ships a commercial FPGA with a fully open-source toolchain. Where these projects each tackle a piece of the puzzle, Aegis is a full-stack, end-to-end open-source FPGA: fabric generation, synthesis, place-and-route, bitstream packing, simulation, and tapeout all live in one project, designed from the ground up for open source. From HDL to GDS, nothing is behind a proprietary wall.

The project generates parameterized FPGA devices with LUT4, BRAM, DSP, SerDes, and clock management tiles, along with everything needed to synthesize user designs onto them and tape out the fabric itself to a foundry via open PDKs and shuttle services like wafer.space.