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v2.0.0 Is Being Produced

A project log for BenchPod

An open hardware bench tool that plugs into your CI: sensor sim, CAN, analog I/O, power control, and a Python SDK with pytest integration

edward-viaeneEdward Viaene 06/19/2026 at 15:000 Comments

Finalized v2.0.0 and ordered it on JLCPCB (the new schematic is under files). A few notes

There are lots of components in v2.0.0, but the board size is the same. On multiple occasions, I wondered about expanding the board or going to more layers. More layers are much more expensive, so a bigger board would be a better solution. Still managed to route everything with the same board size. Almost all the analog path is routed on top. The power at the bottom. For the digital path, it's more mixed, but that should be OK. Here's a screenshot of the wired PCB. Left is analog, middle and right is digital. I removed the ground fill to make it more readable.

Here's the 3D overview. I picked SMA for the analog path (ADC / DAC) and screw terminals for the 4-20mA measurement and output. And yes, this STM32 is huge.

The difficulty with wiring the STM32H563 is that the pins are scattered across multiple protocols. RMII is on all sides, SPI is on all sides, so there's no perfect orientation for the chip. That quickly translates into trying to get all these traces from the ESP32 and RMII down to the STM32 and wiring it up from there.

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