Finalized the ice40 Verilog code to have the capability to run DAC, ADC, and Logic Analyzer at the same time. You can create a waveform and watch the target react on the same timeline, rather than three loosely synced captures.

Moving the trigger into the ice40 fabric is ~1000× tighter than if we'd do it in the server software. We're using an API call to store the data in the 8 MB PSRAM IC, then fire up the DAC/ADC/LA process, which in turn also writes its data back to the PSRAM (we divide the PSRAM for DAC/ADC/LA).

The result is shown in the screenshot below. It's a Logic Analyzer capture with the DAC active, replaying a step motor with a fault. We can see with the logic analyzer at what timing the Device Under Test responds. Pretty good for a $6-8 FPGA chip (it's the ICE40UP5K-SG48I)