So now, RESET is not a level-triggered signal but a sequence.

The previous scheme was to implement weak pull-ups on SC and SD to force it by default. Convenient, simple and no fuss.

But the last log Direct read / flow-through adds a new wrinkle.

The DTAP has several constraints, such as

• It is independent from system reset or system clock, the DTAP may not rely on their presence to initialise.
• All latched values in the chain are unknown and considered random at power up. There is no known/safe way to have a register powering up to a given value (except with the reset input).
• The whole circuit must be able to work when the DTAP is not connected or in use. The system under test must be autonomous and may not rely on the presence of a DTAP controller to initialise.

A pair of weak pull-ups is still "safe" but its actual effect is unknown. Except that in all cases, if you take most cells in the chain, their values will be the same. Which is a condition that can be easily tested.