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• Using an SRAM socket

  Keith • 2 days ago • 0 comments

  This proposed example assumes there is an available 24-pin 2K SRAM socket.

  You will need a module that supports USB FIFO mode.

  The figure below shows the position of the signals in an SRAM and an FTDI UM245H module.

  An old module, it has a mini-USB connector which was quickly replaced by the micro USB and then the USB-C connector. If you buy a modern module, I'd recommend getting a USB-C type which is the most common type in use in 2026. It will probably have a different module pinout, but the principle is the same.

  Most of the signals are an easy join-the-dots exercise. The ground, and data bus.

  Don't connect your 5V rail with the USB 5V rail, unless you are using the USB to power your board.

  The usual case will be to piggyback onto an existing RAM. You do not use the RAM chip select, unless you are replacing the RAM chip with a USB module.

  The read and write signals may be used, but with caution. The USB module I plan to use expects separate strobes like the Z80 uses. The original board might have a 6502 or 6809, which has a read-not-write signal and a phase-2 or E signal. 

  The AC1 pin selects the data in/out or the control/status register. Using A0 is the usual address line, allowing the module to occupy two adjacent bytes. You could use any other address line, if you have  a good reason. 

  Example 1: Ciarcia's Z8001 Trump Card

  The first board that I want to upgrade is a modern remake of Steve Ciarcia's Z8001 board. This has no UART at all, and communicates through a 2K SRAM, dual-ported  to an 8-bit ISA bus. There are counters to turn it into a FIFO buffer. I have no ISA bus, so it would be much better to communicate through USB.

  The USB-FIFO module has its own internal FIFO, so the external counters driving  RAM address lines become redundant. A0 will still toggle between data and status for every odd/even address, which is not wanted. AC1 will thus have to be driven by an address line that differ between the SRAM select and the status register. One way might be to have AC1 connected to the RAM /CE signal. If the 2K RAM is being accessed, it is trying to select FIFO data. If the RAM is not accessed, it is not addressing  FIFO data, and thus the USB module presents its status byte.

  AC0 needs to be active when the board is selecting the 2K RAM socket (the original RAM being removed), or the status byte address.

  The board is still being debugged by the designer, so I am waiting until that is completed.

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