What it does

OpenUSCT reconstructs the interior of a specimen from full-matrix capture on a ring or cylinder array by full waveform inversion — fitting the recorded waveforms against a wave-equation solve — rather than beamforming. It recovers material properties directly, not a brightness image.

The technique is powerful and almost entirely locked inside expensive proprietary scanners and closed toolboxes. OpenUSCT is an attempt at a complete, inspectable, extensible alternative that covers the whole chain.

Three pillars, one system

   +-------------+      +-------------+
   |  HARDWARE   |      | SIMULATION  |
   | array + PCB |      | wave solver |
   +------+------+      +------+------+
          |   same Dataset     |
          |   (HDF5 schema)    |
          +---------+----------+
                    v
          +--------------------+   Python / C++ / MATLAB / GPU
          |  SOFTWARE  (core)  |<-> user algorithms (plugins)
          | imaging, FWI,      |
          | misfits, optimisers|
          +---------+----------+
                    v
                  image

The pillars share a single on-disk format and processing pipeline. A simulated acquisition and a real acquisition both produce the same Dataset — array geometry plus full-matrix-capture channel data in a portable HDF5 file — and the same imaging, FWI and user code runs on either.

That design decision underpins the whole project: the simulator is a digital twin of the instrument, not a parallel codebase that drifts away from it.

>>> INSERT IMAGE HERE: docs/gallery/pipeline-sq.jpg — the three-pillar pipeline. Use the editor's image button, then delete this line.

Run it in your browser

The whole application runs client-side as Python compiled to WebAssembly. On Chrome or Edge, the acoustic acquisition executes on your own GPU through WebGPU, with a live parity check against the CPU reference so you can watch the two agree rather than take my word for it.

jeromegraves.com/openUSCT — no install, nothing to sign up for.

The GUI drives the complete workflow: array and transducer geometry in interactive 3D, the FPGA excitation chain, sample definition (uniform, or a 3D Voronoi polycrystal of anisotropic grains), acquisition with an automatic FPGA RTL capture stage, TFM imaging, and FWI reconstruction with six misfit functionals and two optimisers.

Everything is verified, and here is the evidence

Every physics kernel and gradient carries an explicit check, most to machine precision:

• Acoustic FWI gradient is the exact discrete adjoint (2D and 3D) — finite-difference check, relative error ~0
• C++ and GPU backends match the Python reference — ~1e-15 (C++), ~1e-6 (FP32 GPU)
• Elastic solvers propagate correct P and S speeds — measured against theory, <5%, dispersion-limited and convergent
• Anisotropic solvers (2D, and full 21-component 3D) — measured qP against the analytical Christoffel equation, <1% in 2D
• Six misfit functionals (L2, GCN, envelope, envelope-GCN, traveltime, graph-space optimal transport) — each adjoint source passes a finite-difference gradient check
• Gauss-Newton FWI (matrix-free Born + adjoint) — Hessian-vector product matches FD of the gradient to 1e-7; 4 iterations reach 0.03% misfit where gradient descent reaches 8.5%
• FPGA acquisition datapath — RTL streamed capture bit-exact against the simulated acquisition (Icarus Verilog)

What that buys: grain orientation from one acquisition

With known grain geometry and material, OpenUSCT recovers the 3D c-axis of every grain in a simulated ice polycrystal from a single elastic full-matrix capture — mean axis error 2.0 degrees, worst 3.2 degrees, including a grain started 90 degrees away from truth.

Crystal-orientation fabric is conventionally inferred from bulk sonic velocities. This is a full-waveform approach to the same question.

Status — please read before you ask for photos

The software and simulation pillars run today. The hardware is a complete open design package that has not been fabricated yet.

The acquisition front-end (high-voltage pulser, T/R switch, integrated AFE, Zynq SoC) is designed in KiCad, and the FPGA datapath is written...