Spin FV-1 Emulator

A software emulator for the Spin Semiconductor FV-1 audio DSP.

Abstract

This project is an attempt to develop a software emulator for the Spin Semiconductor FV-1 audio DSP commonly found in guitar pedals and all sorts of digital audio effects hardware. The goal is to emulate the actual FV-1 processor and its instruction set rather than just make another DSP effects library that happens to run FV-1 style effects.

The idea is to eventually be able to take programs written for an actual FV-1, load them into the emulator and run them against either audio files or realtime audio on a PC. This would make it possible to develop, test, debug, and experiment with FV-1 programs without having to constantly program an EEPROM and move back and forth to physical hardware.

Eventually I would also like the emulator to be useful as a debugging and development tool where the internal state of the FV-1 can be inspected while a program is running.

Overview

The FV-1 is a pretty interesting DSP because its architecture is specifically designed around audio effects rather than being a general purpose DSP or microcontroller. The instruction set is relatively small but the instructions themselves can accomplish quite a bit of work.

The FV-1 operates using 24-bit linear audio data and executes 128 instruction cycles for every audio sample. At the normal 48KHz sample rate this works out to about 6 million instructions per second.

The chip has an integrated stereo ADC and DAC, 32 general purpose registers, 32K words of delay memory, three potentiometer inputs, two SIN/COS LFOs, two ramp LFOs, and the DSP core itself.

A program can therefore access audio from the ADCs, process it using the accumulator and registers, read and write delay memory, use the LFOs for modulation, read POT0-POT2 for parameters, and finally send the processed audio to the DAC outputs.

The basic idea of the emulator is to reproduce all of this in software.

At a very high level the process looks something like:

Audio Input -> ADC Registers -> FV-1 Program -> DAC Registers -> Audio Output

For each sample the emulator loads the input audio into the ADC registers, begins executing the FV-1 program, executes the 128 instruction slots, updates the appropriate internal state and delay memory, then collects whatever was written to DACL and DACR as the output sample.

Then it does the whole thing again for the next sample.

Simple enough in theory!!!!!

The fun part is making all of the little details behave like the actual chip.

FV-1 Instruction Set

The first major part of the project is emulating the FV-1 instruction set.

The FV-1 has instructions for working with registers, delay memory, the accumulator, LFOs, branching, filtering, logarithmic/exponential operations, and some other DSP specific operations.

Some examples are:

• RDAX / WRAX
• RDFX
• WRLX / WRHX
• MULX
• RDA / WRA / WRAP
• RMPA
• SOF
• LOG / EXP
• SKP
• WLDS / WLDR
• JAM
• CHO

One thing that makes the architecture interesting is that some of these instructions aren't really equivalent to one normal CPU instruction. A single FV-1 instruction can perform several operations at once.

For example an instruction reading delay memory can read the value, multiply it by a coefficient, add it to the accumulator and update other processor state as part of the same instruction.

So the goal isn't just to parse SpinASM instructions, the goal is to reproduce what those instructions actually cause the FV-1 hardware to do.

Registers and ACC

At the center of most FV-1 programs is the accumulator or ACC.

Most operations either load something into ACC, operate on ACC, or use ACC as part of another calculation. There are also some additional internal states such as PACC and LR that need to behave correctly since FV-1 instructions make use of them.

The processor also contains 32 general purpose 24-bit registers along with special registers representing things like:

• ADCL
• ADCR
• DACL
• DACR
• POT0
• POT1
• POT2
• LFO control registers

Part of the emulator...