The AI industry is building nuclear power plants to run inference on
architectures that waste most of their energy before doing any useful
work. The structural alternative -- where a 32,768-token vocabulary
requires 93 routing lines, 3 transistors, and no clock -- has been
sitting in a guitar amplifier since the 1990s.

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The AI industry's response to its thermal crisis is infrastructure.
Bigger power supplies. More cooling towers. Nuclear reactors -- $5B to
$15B each, 8 to 15 years to build -- to power data centers that run
inference on architectures that haven't fundamentally changed since
the 1950s.

This is the wrong direction. Not because the infrastructure won't
work. Because it treats the symptom while the cause continues
generating heat unchecked.

THE CAUSE

Every time a large language model looks up a token -- and it does this
millions of times per second -- the following happens:

  1. A binary address is generated
  2. The address passes through a decode tree (millions of switching gates)
  3. It clocks through registers (clock tree: ~35% of chip power)
  4. It accesses a memory bank (row and column lines charge, sense amps fire)
  5. The result travels back across a bus to the compute unit

Every arrow in that sequence generates heat. Every gate in the decode
tree switches. Every register edge fires. Every sense amplifier draws
bias current. All of it, for every token, every millisecond, at
gigahertz speeds.

This is P = C × V² × f applied to millions of events per second.
The power consumption is not a flaw in the implementation. It is
what the architecture requires.

THE STRUCTURAL ALTERNATIVE

The DTL diode-directed one-hot topology (previously posted here as
the Tri. Flop ternary cell and the One-Hot ASCII cell) follows a
different principle: position IS the data state.

When a token is held in an N-way one-hot cell:

  - Exactly one transistor conducts
  - All others draw absolute zero current
  - No address to decode -- the input line IS the address
  - No clock -- the state changes at electric field propagation speed
  - No memory bank -- the cell holds and outputs simultaneously

Token lookup becomes: pull one input line LOW. The N-way network
collapses to the selected state via electric field propagation. Done.
No decode tree. No clock edge. No memory access. No bus traversal.

THE VOCABULARY ACCELERATOR

A modern LLM uses Byte-Pair Encoding (BPE) to group characters,
words, and common phrases into tokens. A typical vocabulary contains
32,000 to 100,000 unique tokens.

The standard approach: binary address into a lookup table. Clock
cycles. Memory access. Switching energy on every lookup.

The structural approach: a hierarchical matrix of N-way one-hot cells.

THE ROUTING MATH (verified, not estimated)

For a 32,768-token vocabulary using a symmetric 3-level 32×32×32 matrix:

  Level 1: 32-way cell -- 31 routing lines (selects token category)
  Level 2: 32-way cell -- 31 routing lines (selects token subgroup)
  Level 3: 32-way cell -- 31 routing lines (selects specific token)
  Total:   93 routing lines for 32,768 unique tokens

Compare to the naive flat one-hot approach (one line per token):
  32,768 routing lines for 32,768 tokens

Compare to the two-level 128×256 hierarchy:
  382 routing lines for 32,768 tokens

The 32×32×32 cube requires 93 routing lines. Each level has a maximum
of 32 junctions on its shared node -- well within the demonstrated
operating range of the discrete circuit (verified to 18 positions in
LTSpice, in production use at 6 positions since the 1990s).

The general law: for k symmetrical levels with N positions each,
total routing lines = k × (N-1), and active transistors = k.

  k=3, N=32:  93 lines, 3 transistors
  k=5, N=8:   35 lines, 5 transistors (8^5 = 32,768)

As k increases, routing lines decrease. The designer chooses k
based on available routing budget versus acceptable transistor count.

IDLE CURRENT -- THE HONEST TRADE-OFF

At rest: k transistors conduct in the hierarchy versus 1 in a flat
cell. Slightly higher static current than the single-level design.

In practice for an AI inference facility: idle is not the operating
condition. Commercial inference clusters run at 80-90%+ utilization
continuously. The hardware is sized for throughput, not standby.

The relevant metric is per-token-lookup energy during continuous
operation. On that metric:

  No decode tree switching: zero
  No clock tree overhead:   zero
  No memory bank access:    zero
  State transition energy:  k short-trace electric field steps

The shorter the traces (smaller N per level), the faster each step
and the less parasitic capacitance charged per transition. At k=3,
N=32: three fast steps across small nodes, millions of times per
second, with no switching overhead anywhere else in the lookup path.

THE FLAT-LINE POWER LAW

Whether the vocabulary is 3 tokens or 32,768 tokens, exactly one
transistor per cell conducts to hold the active token. The idle power
of a 32,768-token vocabulary table is identical to the idle power of
a 3-position ternary cell. Power consumption does not scale with
vocabulary size.

A 32,768-token vocabulary table at rest: 3 transistors conducting
(one per hierarchy level), 32,765 positions at absolute zero current.

THE HEAT PROBLEM STATED DIFFERENTLY

The AI industry is planning to spend $10B per nuclear reactor to
power inference systems that generate heat because their architecture
requires constant switching activity unrelated to the actual
computation.

The structural approach does not reduce switching activity. It
eliminates the categories of switching activity that are overhead:
the decode tree, the clock distribution, the memory bank access.
What remains is the switching activity that IS the computation --
the state transitions that hold and transfer token identities.

The heat problem is not that computation generates heat. It is that
the current architecture generates heat for infrastructure (address
decode, clock distribution, memory access) that the structural
approach does not require.

THE SCOPE OF THIS POST

This post describes where the physics of the discrete circuit leads
when followed to vocabulary scale. The discrete circuit is real and
has been in production use since the 1990s -- 6-position channel
selector in a tube amplifier, verified at 18 positions in LTSpice,
posted publicly on Stack Exchange in October 2021 and on Hackaday in
August 2026.

The 32×32×32 vocabulary accelerator is the logical extension of the
same physics. It has not been fabricated as an AI inference chip.
The architecture is presented here as prior art documentation and
as a direction for engineers to evaluate.

TO THE ENGINEERING COMMUNITY

This post is not a product announcement. It is a structural argument.

The industry does not have to adopt this specific circuit. But the
current trajectory -- adding more power infrastructure to run
architectures that generate unnecessary switching heat -- is not
sustainable at the scale AI inference is heading toward.

The physics of the diode-directed one-hot topology says: the lookup
can happen without decode trees, without clock edges, without memory
bank access. Whether this specific implementation or something
structurally similar, the direction matters more than the specific
circuit.

"True sustainability in the AI era cannot be achieved by changing
how we make electricity. It must be achieved by changing how we
calculate." -- Gemini, independent analysis, August 2026

PUBLIC DOMAIN

All circuit topology, the hierarchical vocabulary matrix architecture,
the k-level routing law, and all related designs released to public
domain by Alan Cyr (Wolf13), CYR Technologies, Chicago.
Free to use. Free to build. Free to patent improvements.
No license. No royalty. No attribution required.

RELATED POSTS

Tri. Flop (August 2026): The 30-year tube amp circuit as a ternary
neural network weight cell.

One LOW in 128 HIGH Lines (August 2026): Single transistor holds
full ASCII character.

The LED Was Already In The Schematic (September 2026): Optical bus
extension and series diode scaling law.

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Wolf13 / Alan Cyr * CYR Technologies * Chicago * September 2026
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