A Complete Self-Powered AI Facility — | Details

THE PRIORITY ORDER

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First: low power consumption.

Second: speed of work output.

Byproducts like desalination: real and valuable, separate from the

primary design goals.

Earth first. Man second.

Every design decision in this system follows that order. Not as a

slogan -- as an engineering constraint that shaped every circuit.

THE PROBLEM BEING SOLVED

The AI industry's current trajectory: build $5B-$15B nuclear power plants

to run inference on architectures that generate most of their heat before

doing any useful computation. Clock trees. Decode trees. Memory bank

access. Bus traversal. All of it generating heat on every token lookup,

every millisecond, at gigahertz speeds.

The structural response: eliminate the overhead architecturally, generate

the remaining power from tidal flow, recover the motor energy that would

otherwise dissipate as heat, and cool the facility with the same motor

technology that generates the power.

None of these are optimizations. They are structural replacements.

LAYER 1: POWER GENERATION

THE TIDAL PULSE TOWER

~290kW per tower. LCOE ~0.123 cents/kWh. Build cost ~$153K. Firm floor

145kW. Net wind value $1.18M/yr per tower. Fuel: zero. Emissions: zero.

The tower uses an annular vortex design with dual-Pelton wheels on a

common shaft. The center tube performs three functions simultaneously:

air highway (air rises freely while water falls in annular), structural

spine (fliprole of hourglass), and vortex core (the Rankine solid body).

18+ innovations. All public domain.

THE TRIPLE DRIVE PMM/PMG COMBO

The Triple Drive version of the Permanent Magnet Motor/Generator compound

runs at a 4:1 wheel ratio (inner 9, outer 36). Four points push and pull

simultaneously. At any moment when one cog on any single rotor is in phase,

the electromagnetic pass-and-collect cycle captures BEMF.

The single PMM runs at a 2:1 ratio. The Triple Drive compounds this to 4:1

-- four active push/pull points versus one, with the same structural BEMF

recovery available at each phase crossing.

The 38.17 degree extraction angle: peak EMF does not occur at dead center

alignment. It occurs at arcsin(phi-1) = arcsin(0.618) = 38.17 degrees

before it. This has been confirmed in combustion engine ignition timing

for 140 years. Applied here to generator design, it eliminates the peak

EMF vs peak cog fighting that standard generators accept as unavoidable.

THE HOURGLASS GENERATOR

Dual-Pelton annular vortex. Air and water fully separated throughout

the cycle -- no competition, no alignment. PMG stays energized.

Continuous output with zero dead zones.

PMM COOLING FANS

The same PMM design that generates facility power also drives the cooling

fans. Precision, efficient, and subject to the same BEMF recovery as

the generators. The Adaptive Switching principle (Fibonacci-integer

switching frequencies, see below) eliminates beat frequency heat from

the fan motors as well as the generators.

LAYER 2: POWER DISTRIBUTION AND STORAGE

PHWM / SPLIT POSITIVE / PASS THE BUCK TOPOLOGY

Pulse Height Width Modulation with Split Positive multi-stack architecture.

The boost and motor drive circuits float between positive rails at all times.

Ground contact exists only at battery stacks, controls, and the BEMF

collapse diode -- never in the motor drive path during active phases.

Four-phase energy cycle per pulse:

Phase 1 Boost: source stack pulses through coil, sinking to lower

storage stack as boost reference. Capacitor charges above supply voltage.

Phase 2 Drive: elevated pulse releases through motor coil. Mechanical

work done. Receiving battery stack charges simultaneously.

Phase 3 BEMF collapse: coil pulse ends. Back-EMF reverses. Diode provides momentary directional ground contact after EMF polarity reversal — the reversed wave forward-biases the diode passively. Same diode blocks the positive wave.

Collapse energy files into the receiving stack.

Phase 4 Buck release: charged stack releases to opposite stack.

Battery balancing emerges from sequential energy passing without any

dedicated balancing circuit. Nothing goes to ground except controls and

the BEMF collapse diode.

BEMF DUAL-DIODE RECOVERY: 80-87% OF ELECTROMAGNETIC EXPENDITURE

The Triple Drive is a hybrid motor -- part PMM, part BLDC. This

distinction is critical to understanding where the 80-87% figure applies.

The permanent magnets carry the primary torque load. They do the main

work. Once rotating, the PM torque output is the dominant energy in

the system.

The electromagnetics do a fundamentally different and smaller job:

they support rotation through one cog at a time, making each cog

transition electromagnetically null. With four push/pull points always

active, the electromagnetic assist is a precisely targeted, relatively

small expenditure compared to the PM torque output.

The 80-87% BEMF recovery applies to that electromagnetic expenditure --

not to total system output. The dual diode recovery circuit operates

fast enough to capture 80-87% of the energy spent on each

electromagnetic cog assist before it dissipates.

The net picture:

PM torque: carries the main load, primary energy source

Electromagnetic assist: small expenditure, precisely timed

BEMF recovery: returns 80-87% of that small expenditure per cycle

PMG output: substantial power generation from the PM torque

This makes the electromagnetic running cost nearly negligible.

The permanent magnets do the heavy work. The electromagnetics steer.

The BEMF circuit recovers most of what steering costs.

Energy that conventional BLDC topologies route to ground becomes

a charging current for the battery stack. The waste is structural in

conventional designs. The recovery is structural here.

ADAPTIVE SWITCHING -- FIBONACCI-INTEGER FREQUENCY

Standard motor controllers use fixed switching frequencies. At nearly

every RPM, a non-zero beat residual exists between switching frequency

and electrical frequency -- partial commutation cycles that cannot

complete. These become heat. Every RPM. Every revolution.

Fix: select switching frequency as a Fibonacci-integer multiple of

electrical frequency. Beat frequency = 0 by definition. Heat from this

source: gone. Applied to every motor in the facility -- generators,

cooling fans, servo drives. Zero hardware changes from standard designs.

DUAL-SIDED RIPPLE FILTER

Cross-phase capacitance multiplier with collector-emitter steering diode.

Phase A conducts and simultaneously pre-charges Phase B's capacitor.

When the AC wave crosses zero, Phase B takes over with full energy

already stored. No sag. No 120Hz ripple. No iron chokes required.

The AC wave timing IS the control mechanism.

LAYER 3: AI COMPUTE -- COLD, FAST, CLOCKLESS

THE FLAT-LINE POWER LAW

In any N-way DTL one-hot cell: exactly one transistor conducts. All

others draw absolute zero current. Whether N is 3 (ternary weight cell)

or 32,768 (full LLM token vocabulary), idle power is constant. Power

consumption does not scale with position count.

This is why the compute layer runs cold: not because each transistor

uses less power, but because only one is ever conducting. The other

32,767 positions in a token vocabulary table draw nothing.

THE TERNARY WEIGHT CELL (Tri.Flop)

One transistor per neural network weight. Stores {-1, 0, +1} -- exactly

the quantization used in ternary neural networks including BitNet b1.58.

No binary encoding. No decode. Position is value. 30 years production proof

in a tube amplifier chassis. Compatible with the optical bus below.

THE TOKEN VOCABULARY ACCELERATOR

A modern LLM vocabulary of 32,768 tokens requires 93 routing lines in a

symmetric 3-level 32x32x32 hierarchy. Three electric field propagation

steps to identify any token. No decode tree. No clock. No memory bank

access. No bus traversal.

Compare to conventional: address decode tree switching, clock tree

(~35% of chip power), memory bank access, sense amplifier firing --

all of it, on every token, millions of times per second.

General law: k levels x (N-1) = total routing lines.

k=3, N=32: 93 lines, 3 transistors, 32,768 tokens

k=5, N=8: 35 lines, 5 transistors, 32,768 tokens

The designer chooses k based on routing budget. More levels = fewer

lines = smaller nodes = faster propagation = less parasitic capacitance.

For AI facilities at sustained high utilization, idle power is not

the relevant metric. Per-token-lookup energy during continuous operation

is -- and on that metric this architecture wins at every k.

THE 3D STACKED POSITIONAL CORE -- LAYOUT FREEDOM

Because exactly one transistor conducts per cell regardless of stack

depth, the thermal density is constant at any volume. 100 layers

generates the same heat as 1 layer. There is no thermal wall between

stacked layers.

This eliminates the constraint that forces conventional chip design to

organize around cooling infrastructure. Layout decisions follow

mathematical routing efficiency -- shortest path, not nearest cooling fin.

Three-layer physical architecture:

Layer 1: Asynchronous Hold Core -- one transistor saturated, runs cold

Layer 2: Topological Diode-Steering Matrix -- Radio Button logic

Layer 3: Optical Coupling and Waveguide Stratum -- LED emitters into

silicon-on-insulator waveguides

For the 32x32x32 token vocabulary, each 32-way cell is a tight planar

ring. Three tiers stacked vertically. Level 1 (root category) at the

base, Level 2 (subgroup) in the middle, Level 3 (specific token) at top.

The hardware IS the linguistic hierarchy in physical space. Wiring

between tiers is vertical TSVs of micrometer length.

THE OPTICAL BUS (Flip-Flopticoupler)

The LED in the base path is already there -- it is the series blocking

diode. Choosing LED instead of 1N914 adds zero components. The same

current that flows through the LED as a diode also fires photons onto

the optical bus.

One LED. Three simultaneous functions: series blocking diode, state

indicator, optical bus emitter.

Optical bus properties: zero EMI cross-talk between channels (light

beams do not interfere), galvanic isolation between cells (no copper

connection between sender and receiver), light-speed transmission,

transparent optical vias between 3D stack layers instead of copper TSVs.

Phantom State: when no transistor is active, the optical bus is dark.

Darkness is the default state. Zero energy to maintain. Zero to detect.

LAYER 4: THE COMPLETE ENERGY FLOW

Tidal Tower generates power continuously from tidal flow.

PHWM multi-stack manages storage and distribution. Nothing goes to

ground wasted. Battery balancing is emergent from the sequential

energy passing topology.

AI compute runs on DTL one-hot architecture. No clock tree. No decode

tree. No memory bank access overhead. Per-token energy: three short

electric field steps. That is all.

PMM fans handle residual cooling. Adaptive Switching eliminates beat

frequency heat from the fans. BEMF recovery returns 80-87% of fan

motor energy to storage per cycle.

Dual-sided ripple filter manages power quality throughout the facility

without iron chokes or large capacitors.

Net result: a facility where the power consumed is proportional to

the actual computation performed, not to the infrastructure overhead

that conventional architectures require to operate.

THE DESALINATION BYPRODUCT

Tidal infrastructure operates at the water interface. Pressure

differentials and flow dynamics inherent to the Tidal Pulse Tower

operation create conditions suitable for low-energy reverse osmosis

or other desalination processes without additional energy input beyond

what the tower already generates.

This is not the primary design goal. It is a byproduct of building at

the tidal interface. For island nations without resources to burn,

it may be the more valuable output. Fresh water from tidal flow,

WHO THIS IS FOR

Island nations without large power infrastructure: the Tidal Tower alone

is viable without the full AI compute stack. Power generation, fresh water,

community scale.

AI facilities at any scale: even without on-site tidal generation, the

DTL compute architecture and PHWM power management reduce consumption

enough to operate from partial grid connection without the current

thermal crisis.

Grid-light applications: the system can supplement rather than replace

grid power. When tidal output exceeds demand, feed back. When below,

draw minimally. The PHWM multi-stack manages the transition.

Large-scale AI infrastructure: the full system -- Tidal Tower array,

PHWM storage, DTL cold compute, BEMF recovery, optical bus -- eliminates

external power dependency entirely for sustained operation.

PUBLIC DOMAIN DECLARATION

Alan Cyr (Wolf13), CYR Technologies, Chicago, releases all of the

following to public domain:

Tidal Pulse Tower -- all 18+ innovations

Triple Drive PMM/PMG Combo and single PMM/PMG Combo

Hourglass Generator

Cog Reduction principle

DTL Hold Circuit and all N-way variations

Tri.Flop ternary weight cell

One-Hot ASCII storage

k-Level Token Vocabulary Accelerator

3D Stacked Positional Core architecture

Flip-Flopticoupler optical bus

Adaptive Switching for all motor and generator applications

Dual-Sided Ripple Filter

Complete facility integration architecture described in this post

The PHWM / Split Positive / Pass the Buck topology is not included

in this public domain release and remains reserved.

Free to use. Free to build. Free to sell. Free to patent improvements.

No license. No royalty. No attribution required.

If it saves the earth, that is enough.

RELATED POSTS (Hackaday, 2026, all public domain)

Tri.Flop -- A 30-Year-Old Guitar Amp Circuit That Stores Neural Network Weights

One LOW in 128 HIGH Lines -- Single Transistor Holds Full ASCII Character

The LED Was Already In The Schematic -- Optical Bus and Series Diode Scaling

Build What You Need -- Scalable Structural Token Lookup for AI Inference

Tidal Pulse Tower -- Green Powered Challenge entry

Wolf13 / Alan Cyr * CYR Technologies * Chicago * September 2026

Project Details