Open-source FPGA debug cores — in native Verilog and VHDL — that you drop into any design to see and control what's happening inside your FPGA over JTAG: no extra board pins, no soft CPU, no vendor lock-in.

Think of it as an open, vendor-neutral alternative to ChipScope / SignalTap / Reveal that works the same way across AMD/Xilinx, Intel/Altera, Lattice, Gowin, Microchip and Efinix parts, plus a Python / CLI / GUI host stack on top.

Four small RTL cores, all driven over JTAG:

ELA — Embedded Logic Analyzer — capture internal signals into a waveform with flexible triggers, and export to VCD / CSV / JSON.
EIO — Embedded I/O — read and drive fabric signals live at runtime.
EJTAG-AXI — a JTAG-to-AXI4 master bridge for memory-mapped bus access.
EJTAG-UART — a JTAG-to-UART console bridge.

Check the github: https://github.com/lcapossio/fpgacapZero