(the silicon phase, up to the moment before Quartus)

Slide 01 — Build Log #3 — the silicon phase, up to the moment before Quartus

Five days after Log #2 the repository has a hw/ directory, a Layer 4 with six phase reports, and a discrepancy ledger twenty-one rows long. None of it was written by the amanuensis who writes these logs. It was written by a second, context-isolated AI — Claude Code — working from a brief, in a workspace of four repositories, stopping at the end of every phase for the architect to read and rule. The architect ruled four times: September 28, 29, 30 and October 1. The reports are in the repository; here is what they say.

Slide 02 — Four offices, one repository: brief, phase report, ruling, next phase

The rule of the brief. Everything the hardware had to agree with already existed: an instruction-level machine for the Formation, a sweep-level oracle for the sequencer, the customer's oracle for the pipeline, and the timing core's own testbenches. The brief's one hard rule: never edit a golden model to make hardware pass. Five days later, not one model has been edited. Where hardware and model disagreed, the report says so and a ledger row explains why. And to show the comparisons bite, every phase breaks its own hardware on purpose: twenty single defects in the datapath, eleven in the sequencer, more in the pipeline and the switch — each must make the cosimulation fail, and each did. The game-theoretic name for this is mutation testing, which is older than most of the people doing it (Lipton, 1971; DeMillo, Lipton and Sayward, 1978). We just call it does the test bite?

Slide 03 — The one hard rule of the brief

Slide 04 — Does the test bite? Planted defects that must make the cosimulation fail

Slide 05 — Six phases against their oracles — every SILICON cell still pending

Phase 1 — the timing core, on a copy. The frozen PTSG-Core stays frozen. A working copy gained one port and two wires — the stay_value pin from Log #2 — and ran in lockstep with the original for 600,000 clocks with the pin silent: zero mismatching clocks, and VCDs identical on 579,164 value changes. The one thing that could go wrong (reading a registered copy of the pin beside a raw zero test, which turns a one-clock change into an 8,192-tick runaway) was built once, in a testbench, to prove the test catches it.

Slide 06 — Phase 1 — the timing core, on a copy, in lockstep with the original

Phase 2 — the first RTL of the master ISA, ever. The master's data-processing ISA has lived in prose and in a Python contract until now; the L2 Formation is its first hardware. Driven one instruction per clock exactly as the Core drives it, the datapath is bit-identical to the instruction-level model on 3,914 cases — the three window programs, the thirteen negative cases, and thousands of random instruction sequences drawn from the contract. The bit-level encoding, which the master deliberately left open, is published once as JSON, and both the Verilog decoder and the assembler are generated from it.

Slide 07 — Phase 2 — the first RTL of the master ISA; one encoding, two generated tools

Phase 3 — Duff's device at 48 kHz. Log #2 promised that the Core would repeat packets either by re-entering one packet body (R2) or by playing eight unrolled positions (R1). The Core as built cannot do R2 without a clock: a queued loop never reads its count from outside. So Claude Code did what Tom Duff did in 1983 — unrolled the loop and jumped into the middle of it. The housekeeping window computes a jump target from P, the number of packets, and the Core enters the unrolled chain at position 8 − P. No conditional branch anywhere, nothing saved on the Core's stack, zero clocks between packets, and the first packet's Stay Set one clock after the strobe (the pipeline sees it one clock later still). Against the sweep oracle: 36,000 sweeps, 128,321 packets, 54 million bins at the 100 MHz budget, and the same again at 50 MHz — identical, down to the eight words of every bundle and the Stay value at every Stay.

Slide 08 — Phase 3 — Duff's device: jump into the unrolled chain at position 8 − P

The same phase found a bug in the Core's insertion handshake — the Core takes a still-held request twice, waits on a stack that is not there, and never reaches its own halt. The Formation now withdraws its request one clock earlier, and the finding went upstream as a bug report. A synthesizer's testbench catching a timing core's handshake is exactly what a second office is for.

Slide 09 — Phase 3 — identical to the sweep oracle, and one bug sent upstream

Phase 4 — the pipeline, bit-exact. The L1 difference engine, the log-domain amplitude with its exp2 unit, the output path with its master gain, the 48 kHz strobe at 2,083 and 2,084 clocks: bit-exact against the customer's oracle, imported unchanged. The customer's own end-to-end numbers reproduce: a σ = 71 Gaussian plays 927 audible bins; the master gain reaches −60 dB in 1.0000 s; the latency from sweep start to the first left-channel MSB on the wire is 21.484 µs. Sixteen DSP blocks per module, as the customer estimated. One thing the customer's oracle never modelled — the sine itself — was written as a reference model here and, by the architect's ruling, became the official specification. (Its coefficient table, taken literally, would have left an 11th-order term at two LSB. It was noticed, measured, and ruled.)

Slide 10 — Phase 4 — the pipeline, bit-exact; the customer's numbers reproduce

Phases 5 and 6 — a switch, a board top, and eight bounds written before any run. The minimal input switch (the ROM with the test origin, and a host path that a human drives from the Quartus editor), then the DE10-nano top: HDMI audio through the ADV7513, I²S, a 720p carrier, three PLLs. On a board-level bench the eight evidence items the brief demanded are all green at both budgets: g = 0, wake in 2, the packet floor at 30 (so the profile's N_MIN = 32 holds), the masked block copy at exactly its bound of 10 clocks, the full-load sweep asleep with 18 clocks to spare, every error code once with the pipeline silent after it, 534 of 534 bundles equal to prediction, and a first sound — the test origin, then one GO that puts C5 and E5 on the left and E5 and G5 on the right. The spectrum matches the model. We have not heard it yet.

Slide 11 — Phases 5–6 — the input switch and the DE10-Nano board top

Slide 12 — Eight bounds, written before any run — green at both budgets

Slide 13 — First sound on the bench: one GO, two channels

Two realistic decisions. The architect ruled schedule first: if 100 MHz is at all difficult, the first silicon runs at 50 MHz with 1,008 bins per module — the 2,048 of the headline is the 100 MHz number, and it waits for timing closure. And the host path is ISSP over JTAG, edited by hand, which overrides the customer's own reference and is recorded as such. Both are the kind of decision an architect makes and an amanuensis records.

Slide 14 — Two realistic decisions

The honest footnote. Every row of the evidence table carries the word pending in its SILICON column. Everything above is RTL simulation and a board-level bench; the Fitter has not run, the fractional PLLs have not been placed, and the instruction memory's half-cycle read — the Core's known critical path — has not met 100 MHz or failed to. That is what the next log is for. Measured, not promised — and the measuring instrument is finally plugged in.

Slide 15 — The honest footnote: every SILICON cell says pending

Twenty-one disagreements between documents and silicon-to-be, filed and not one fixed in silence; four offices — a human architect and three AI amanuenses, each in its own session — and a repository that tells you, phase by phase, what was expected before it was observed. Allow us this much pride before the compile.

Slide 16 — Twenty-one disagreements, filed. Not one fixed in silence.

(JA 要旨: Log #2 から五日。第 3 層に hw/、第 4 層に六段階の報告書、食い違い台帳二十一行。書いたのは別の AI（Claude Code）で、段階ごとに止まり、アーキテクトが四回裁定した。黄金モデルは一度も書き換えず、各段階で自分のハードを故意に壊して試験が噛むことを示した（ミューテーション試験、1971 年）。Core は写しに一ポート二配線を足し 60 万クロックで原本と完全一致。Formation データパスはマスター ISA 初の RTL で、3,914 ケースでモデルとビット一致。パケットの繰り返しは Core が無間隙の再入を持たないため、1983 年の Duff's device と同じく展開した連鎖の途中へ跳び込む形で g = 0、起床 1 クロック。掃引オラクルと 36,000 掃引・5,400 万ビンで同一。Core の挿入ハンドシェイクのバグも発見し上流へ報告。L1 と出力路は顧客オラクルとビット一致、σ = 71 で 927 ビン、遅延 21.484 µs、DSP 16 個。基板レベルの試験台で証拠 8 項目がすべて緑、最初の音は C5・E5・G5 の三和音——ただしまだ耳では聴いていない。現実的判断は二つ：日程優先で 50 MHz・1,008 ビン、ホスト経路は ISSP。すべての行の SILICON 欄はまだ「pending」。次のログは Fitter の結果から。)

(Log #1 and Log #2 stand as dated records; this log describes the state on 2026-10-02, before the first Quartus compile.)