(first sound, a Dirichlet kernel, and five captures that matched to the clock)

On October 3rd the board made a sound. On October 4th it made the sound it was supposed to make — and the difference between those two sentences is this log.

Slide 2 · Two days, two sounds

The first sound. The second Quartus fit still missed its clock by seven nanoseconds at the slow corner, but at room temperature a bitstream that misses timing often runs anyway, and the architect could not wait. HDMI audio extractor, oscilloscope, loudspeaker. The report that came back read: a waveform based on a 1 kHz sine, amplitude-modulated with a period of 250 ms, with slow changes, very stable.

Nobody had told the architect what to expect. So the amanuensis worked it out afterwards, from the integers in the ROM. The test origin is one packet of 1,008 partials, equal in amplitude and in phase at the GO, from 996.000 to 999.939 Hz, 3.912 millihertz apart.

Slide 3 · The test origin: one packet, 1,008 partials

The sum of equally spaced, phase-locked sines is a textbook object: a carrier at the centre frequency, 997.97 Hz, times the envelope |sin(πN·Δf·t) / sin(π·Δf·t)| — the Dirichlet kernel, the function Dirichlet introduced in 1829 to prove when a Fourier series converges.

Slide 4 · The Dirichlet kernel

Its envelope has a null every 1/(N·Δf) = 253.62 ms, and it repeats every 1/Δf = 255.65 s, four minutes and 15.7 seconds: loudest right after the GO, sixty decibels down at two minutes eight, loud again at 4:15.7.

Slide 5 · One period, 4:15.7

A physicist would call this a mode-locked laser — a comb of equally spaced modes with locked phases emits a pulse train whose period is the inverse of the mode spacing — slowed from picoseconds to four minutes.

Slide 6 · The same math as a mode-locked laser

The next day, with the gain switches set as the model assumed, the architect wrote: a perfectly beautiful Dirichlet kernel, its main lobe about every 4 minutes 15 seconds. The prediction had been in the repository since the evening before.

Slide 7 · “a perfectly beautiful Dirichlet kernel”

Forensics on forty million sweeps. The same first-day board also yielded a SignalTap capture of the timing core's state and the I²S pins — 8,192 clocks of it, somewhere in a thirteen-minute run. Where, exactly? The closed form of the kernel answered: the eight audio words on the wire fit the model to the bit at sweep 39,684,738 after the GO — thirteen minutes 46.8 seconds in — at gain G = 0 (the switches were still down), with no other setting coming close. Two things follow. The I²S path, the ADV7513 configuration and the whole chain from ROM to HDMI are bit-exact. And the packet's window program, which rewrites three phase words in the store every sweep, had done so forty million times without a single miss on a bitstream that did not meet timing. (Please do not try this at 85 °C. We didn't.)

Slide 8 · Forensics on forty million sweeps

Closing the clock, the old-fashioned way. The path that failed was not ours: the timing core's instruction memory reads on the falling edge, and at 50 MHz with a symmetric clock the read side had 10 ns — two short. No SDC relaxation, no pipelining of the frozen core. The 50 MHz clock now runs 30 % high: 6 ns high, 14 ns low. The read side gets 14 ns, the address side keeps 6, the analyzer sees the real waveform, and the third fit closes with +0.978 ns to spare and every clock meeting. Two-phase clocking with unequal phases is older than FPGAs; sometimes the right fix is the one your grandparents used.

Slide 9 · Closing the clock, the old-fashioned way

Five captures, written first. Each SignalTap capture had its expected values in the repository before the trigger was armed — from RTL simulation, and before that from the oracle. On October 4th the architect took them all. The gap between packets: 0. The strobe to the first packet: 2 clocks. The shortest packet the core can play with our 25-instruction window: 30 clocks, so the profile's limit of 32 holds. A full masked copy of eight blocks and a sweep word: 10 clocks. A full-load sweep of 1,008 bins: 1,023 of the 1,041 clocks a 48 kHz sample allows at 50 MHz. Forty-five parameter bundles and twelve output banks equal to the model, bit for bit.

Slide 10 · Five captures, written first

And each of the five error codes, injected on purpose: the code, then silence from the pipeline, then the core halted at its trap — 9, 1,005, 1,001, 11 and 1,000 clocks later, exactly as simulated.

Slide 11 · Five error codes, injected on purpose

One GO from the host produced a C-major chord, C5 and E5 on the left, E5 and G5 on the right.

Slide 12 · One GO, one C-major chord

Every value measured on the board equals the value written before the capture.

Along the way the board taught us things no simulator had: the host script opened a JTAG session and then asked for the instance list, which the tool refuses while a session is open; PowerShell's > writes UTF-16; SignalTap's storage qualifier, named as a pin instead of a node, quietly stored everything. Each is a ledger row now, with its fix and its test.

Slide 14 · What the board taught us

Two decisions, one direction. The timing core and the Formation will stay at 50 MHz; the pipeline runs at 100 MHz, two bins per Formation clock, with a half-bit under the Stay counter — so the headline 2,048 per module returns, at the price of even packet lengths and a 64-bin minimum. And every packet's own sum will go into a small two-bank table every sample, readable by every Formation two samples later: the first feedback route at the instruction level, and the one the Kuramoto Mode specification — already written, with its critical coupling K_c = 4γ/π on paper — will read its mean field from.

Slide 15 · Two decisions, one direction

The honest footnote. This is 1,008 oscillators per module at 50 MHz. The 2,048 figure is the next build, not this one. And a Dirichlet kernel, however beautiful, is a linear sum: the self-organized part of the story has not sounded yet. What has sounded is the control plane that will carry it — predicted, then heard.

Slide 16 · The honest footnote

This week the board goes to an open house, with its 4:15.7 and the prediction that preceded it.

Slide 17 · Predicted, then heard.

(JA 要旨: 10 月 3 日に初音、10 月 4 日に「鳴るべき音」が鳴った。タイミング未収束のビットストリームで架構が聴いた「1 kHz・250 ms の AM・ゆっくり変わる・非常に安定」を、祐筆が ROM の整数から後追いで解いた——1,008 本の等間隔・同位相の正弦波の和はディリクレ核（1829 年、フーリエ級数の収束証明の道具）で、ヌルは 253.62 ms ごと、周期は 1/Δf = 255.65 s＝4 分 15.7 秒。モード同期レーザーのパルス列を四分周期まで減速したものと同じ数学。翌日、架構は「完璧に美しいディリクレ核、主ローブはほぼ 4 分 15 秒ごと」と記した。初日の SignalTap 取得は閉形式から「GO 後 39,684,738 掃引目」と同定され、I²S の 8 語がビット一致——4,000 万回の位相更新がタイミング未収束でも一度も落ちていなかった（85 ℃では試していない）。失敗していた経路は凍結 Core の命令メモリの立下り読出しで、50 MHz のクロックを 30 % High にして読出し側に 14 ns を渡し、第 3 フィットが +0.978 ns で収束。五つの取得はすべて取得前に期待値が書かれ、g = 0、起床 2、床 30、BCP 10、満載 1,023/1,041、45 バンドル・12 バンクが一致、五つのエラーコードが各一回、GO 一発の C メジャー。基板が教えた三つの落とし穴も台帳に。次は PTSG 50 MHz・L1 100 MHz の半速 Stay と、パケット出力表。正直な脚注：これは 50 MHz・1,008 本であり、ディリクレ核は線形和で、自己組織化の部分はまだ鳴っていない。)