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SARV A Risc-V

SARV is an open-source, six-stage RV32 processor with configurable ISA extensions, caches, and embedded-system support.

amirreza-torabiAmirreza Torabi
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The source code, design files, and ongoing development are available on GitHub:

https://github.com/Sarst04/SARV

Contributions, technical discussions, and feedback on processor architecture, RTL implementation, verification, and embedded-system integration are welcome.

SARV is an evolving hardware-design project, and its features and implementation details may change as development progresses.

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