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First simulation run

A project log for TMS9900 compatible CPU core in VHDL

Retro challenge 2017/04 project to create a TMS9900 compatible CPU core. Again in a month... Failure could be an option...

erik-piehlErik Piehl 04/03/2017 at 12:370 Comments

After working on the CPU core a few hours to get started, I was able to complete my initial objectives:

Below is a picture from one of the first simulation runs. There are two instructions, like this:

5678 JMP >567A   * effectively a NOP
567A JMP >5678   * branch back to previous line

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