James OtsI have my computer working again. The main problem was the ROM_BOOT_N signal, which I had coming into the CPLD on GTS1, which is pin 3. The CPLD didn't seem to be reading this signal (I don't know if it's badly soldered, if the input is blown, or if I'm not supposed to use GTS1 for some inexplicable Xilinx reason), and so the computer was always trying to boot from the ROM. I've now moved it onto GTS3 (pin 1), and it seems to be working. And I'm able to write to the ROM if I do it with a PEEK command in my monitor, but not with a COPY. So I need to debug that.
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Actually, this makes complete sense. I was trying to copy from the ROM to the ROM. But after writing a byte to the ROM, a read becomes a query to see if the read has completed, so the rest of the bytes that it copies are all just status bytes. If I copy 64 bytes from RAM to the ROM then it is fine. I need to write a rom copy routine though, which will wait after each 64 byte block for the write to complete before continuing.
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