The A1,D1,A2,D2,A3,D3 registers emulate a sort of multi-ported memory. However there is only one standard memory chip (or it looks like that with several chips to emulate a 16-bits datapath).

The circuitry is a bit unusual and requires some MUXes here and there because the result bus can go to the address bus or the data bus of the SRAM chip(s).

There are two cases to consider:

• SRAM Write : when writing to the D1/D2/D3 register, so the result bus goes to the Data bus AND the corresponding register latch. The address bus is then controlled by the corresponding A1/A2/A3 register.
• SRAM Read : the result goes to a A1/A2/A3 register and the address bus. The D1/D2/D3 register is written by the SRAM's data bus.

So basicly, the SRAM's address bus is selected between the RES bus or A1/A2/A3, that's a MUX4. 8 pieces of 74HC153/253 are required. The 253 adds a tristate output that will be handy for an eventual takeover of the bus for external inspection...

The SRAM's data bus is bidirectional and a MUX won't work. There are 3 registers connected to the data bus (D1/D2/D3) that can be written by the SRAM or the RES. The SRAM has tristate output and must be isolated from the RES bus. The solution is to separate them with a pair of 74HC573 or 74HC245. The /OE of one is the opposite of the other's /OE to prevent contention.

So to sum up: the Data RAM part of the system contains

• 64K × 16 bits of SRAM (probably a pair of Pentium Cache SRAM because they are fast and already available)
• 2×245 for result bus isolation
• 6×574 for D1/D2/D3 (let's use 574 instead of 573 because a transparent latch could wreak havoc in the pipeline if the Dx is itself already a source of the address, such as in a linked list)
• 8×253 for address selection

That's already a nice board, with 48 bits going from the registers, 48 bits going TO the registers, 16 bits from the result bus and the untold number of control signals...